Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz Data and Non-volatile Program and Data Memories – 2/4K Bytes of In-System Self Programmable Flash • Endurance 10,000 Write/Erase Cycles – 128/256 Bytes In-System Programmable EEPROM • Endurance: 100,000 Write/Erase Cycles – 1
1. Pin Configurations Figure 1-1.
ATtiny2313A/4313 will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATtiny2313A/4313 as listed on page 61. 1.1.4 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit).
2. Overview The ATtiny2313A/4313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313A/4313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram XTAL1 XTAL2 PA0 - PA2 PORTA DRIVERS DATA DIR. REG.
ATtiny2313A/4313 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
3. About 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation.
ATtiny2313A/4313 4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.1 Architectural Overview Figure 4-1.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register.
ATtiny2313A/4313 The AVR Status Register – SREG – is defined as: Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
• Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 4-2. AVR CPU General Purpose Working Registers 7 0 Addr.
ATtiny2313A/4313 In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack.
Figure 4-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 4-5.
ATtiny2313A/4313 the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present.
4.7.1 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles.
ATtiny2313A/4313 5. Memories This section describes the different memories in the ATtiny2313A/4313. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATtiny2313A/4313 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 5.1 In-System Reprogrammable Flash Program Memory The ATtiny2313A/4313 contains 2/4K bytes On-chip In-System Reprogrammable Flash memory for program storage.
5.2 SRAM Data Memory Figure 5-2 shows how the ATtiny2313A/4313 SRAM Memory is organized. The lower 224/352 data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O memory, and the next 128/256 locations address the internal data SRAM.
ATtiny2313A/4313 Figure 5-3. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction 5.3 Next Instruction EEPROM Data Memory The ATtiny2313A/4313 contains 128/256 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the erase/write operation. Both the erase and write cycle are done in one operation and the total programming time is given in Table 5-1 on page 22. The EEPE bit remains set until the erase and write operations are completed. While the device is busy with programming, it is not possible to do any other EEPROM operations. 5.3.
ATtiny2313A/4313 5.3.6 Program Examples The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
ATtiny2313A/4313 5.4 I/O Memory The I/O space definition of the ATtiny2313A/4313 is shown in “Register Summary” on page 252. All ATtiny2313A/4313 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
5.5.2 EEDR – EEPROM Data Register Bit 7 6 5 4 3 2 1 0 EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0x1D (0x3D) EEDR • Bits 7..0 – EEDR7..0: EEPROM Data For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register.
ATtiny2313A/4313 When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. • Bit 1 – EEPE: EEPROM Program Enable The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM. When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting.
6. Clock System Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 33. Figure 6-1.
ATtiny2313A/4313 6.2 Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 6-1. Device Clocking Select Device Clocking Option CKSEL3..
Figure 6-2. External Clock Drive Configuration NC XTAL2 EXTERNAL CLOCK SIGNAL XTAL1 GND When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 6-2. Table 6-2. Start-up Times for the External Clock Selection SUT1..
ATtiny2313A/4313 Reset Time-out. For more information on the pre-programmed calibration value, see the section “Calibration Byte” on page 181. Table 6-3. Note: Internal Calibrated RC Oscillator Operating Modes CKSEL3..0 Nominal Frequency 0010 4.0 MHz 0100 8.0 MHz(1) 1. The device is shipped with this option selected. When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 6-4. Table 6-4.
6.2.5 Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 6-3 on page 28. Either a quartz crystal or a ceramic resonator may be used. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment.
ATtiny2313A/4313 Table 6-7. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 SUT1..
6.4 Clock Output Buffer The device can output the system clock on the CLKO pin. To enable the output, the CKOUT fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system. Note that the clock will not be output during reset and that the normal operation of the I/O pin will be overridden when the fuse is programmed. Any clock source, including the internal RC Oscillator, can be selected when the clock is output on CLKO.
ATtiny2313A/4313 The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.
Table 6-9.
ATtiny2313A/4313 7. Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 7.
parator Control and Status Register” on page 167. This will reduce power consumption in Idle mode. 7.1.2 Power-Down Mode When the SM1:0 bits are written to 01/11, the SLEEP instruction makes the MCU enter Powerdown mode. In this mode, the Oscillator is stopped, while the external interrupts, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, an external level interrupt on INT0 and INT1, or a pin change interrupt can wake up the MCU.
ATtiny2313A/4313 Peripheral shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. See “Effect of Power Reduction” on page 203 for examples. In all other sleep modes, the clock is already stopped. 7.4 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital Input Disable Register (DIDR). See “DIDR – Digital Input Disable Register” on page 168 for details. 7.5 7.5.1 Register Description MCUCR – MCU Control Register The Sleep Mode Control Register contains control bits for power management.
ATtiny2313A/4313 • Bit 2 – PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. • Bit 1 – PRUSI: Power Reduction USI Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When waking up the USI again, the USI should be re initialized to ensure proper operation.
8. System Control and Reset 8.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 8-1 shows the reset logic.
ATtiny2313A/4313 8.2 Reset Sources The ATtiny2313A/4313 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT) • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length when RESET function is enabled • Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled • Brown-out Reset.
8.2.2 External Reset An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width (see “System and Reset Characteristics” on page 198) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay counter starts the MCU after the Time-out period – tTOUT – has expired. Figure 8-4.
ATtiny2313A/4313 8.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. See “Interrupts” on page 47 for details on operation of the Watchdog Timer. Figure 8-6. Watchdog Reset During Operation CC CK 8.3 Internal Voltage Reference ATtiny2313A/4313 features an internal bandgap reference.
The Watchdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down. To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse WDTON as shown in Table 8-1 See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 42 for details. Table 8-1.
ATtiny2313A/4313 a. In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence b. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant 8.4.2 Code Example The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g.
8.5 8.5.1 Register Description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 7 6 5 4 3 2 1 0 0x34 (0x54) – – – – WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 MCUSR See Bit Description • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313A/4313 and will always read as zero.
ATtiny2313A/4313 the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after each interrupt. Table 8-2. Watchdog Timer Configuration WDE WDIE Watchdog Timer State Action on Time-out 0 0 Stopped None 0 1 Running Interrupt 1 0 Running Reset 1 1 Running Interrupt • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled.
Table 8-3. WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V 0 0 0 0 2K cycles 16 ms 0 0 0 1 4K cycles 32 ms 0 0 1 0 8K cycles 64 ms 0 0 1 1 16K cycles 0.125 s 0 1 0 0 32K cycles 0.25 s 0 1 0 1 64K cycles 0.5 s 0 1 1 0 128K cycles 1.0 s 0 1 1 1 256K cycles 2.0 s 1 0 0 0 512K cycles 4.0 s 1 0 0 1 1024K cycles 8.
ATtiny2313A/4313 9. Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny2313A/4313. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. 9.1 Interrupt Vectors The interrupt vectors of ATtiny2313A/4313 are described in Table 9-1 below Table 9-1. Reset and Interrupt Vectors Vector No.
The most typical and general setup for the Interrupt Vector Addresses in ATtiny2313A/4313 shown below: Address Labels Code Comments 0x0000 rjmp RESET ; Reset Handler 0x0001 rjmp INT0 ; External Interrupt0 Handler 0x0002 rjmp INT1 ; External Interrupt1 Handler 0x0003 rjmp TIM1_CAPT ; Timer1 Capture Handler 0x0004 rjmp TIM1_COMPA ; Timer1 CompareA Handler 0x0005 rjmp TIM1_OVF ; Timer1 Overflow Handler 0x0006 rjmp TIM0_OVF ; Timer0 Overflow Handler 0x0007 rjmp USART0_RXC ; USAR
ATtiny2313A/4313 9.2.1 Low Level Interrupt A low level interrupt on INT0 or INT1 is detected asynchronously. This means that the interrupt source can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted in all sleep modes except Idle). Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt.
9.3 9.3.1 Register Description MCUCR – MCU Control Register The External Interrupt Control Register contains control bits for interrupt sense control.
ATtiny2313A/4313 • Bits 2..0 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control bits (ISC11 and ISC10) in the External Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT1 is configured as a level interrupt. • Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
ATtiny2313A/4313 • Bits 7:3 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bits 2..0 – PCINT10..8: Pin Change Enable Mask 10..8 Each PCINT10..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT10..8 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT10..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 9.3.
10. I/O-Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability.
ATtiny2313A/4313 10.1 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 10-2. General Digital I/O(1) PUD Q D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET WRx WPx RRx SLEEP SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: 10.1.
10.1.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 10.1.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur.
ATtiny2313A/4313 Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge.
important, it is recommended to use an external pull-up or pulldown. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output. 10.1.7 Program Examples The following code example shows how to set port A pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with a pull-up assigned to port pin 4.
ATtiny2313A/4313 10.2 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. In Figure 10-5 below is shown how the port pin control signals from the simplified Figure 10-2 on page 55 can be overridden by alternate functions. Figure 10-5.
Table 10-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 10-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 10-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
ATtiny2313A/4313 10.2.1 Alternate Functions of Port A The Port A pins with alternate function are shown in Table 10-3. Table 10-3.
Table 10-4 relates the alternate functions of Port A to the overriding signals shown in Figure 105 on page 59. Table 10-4. Signal Name Overriding Signals for Alternate Functions in PA2..
ATtiny2313A/4313 Table 10-5.
(one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. • PCINT4: Pin Change Interrupt Source 4. The PB4 pin can serve as an external interrupt source for pin change interrupt 0. • Port B, Bit 5 – DI/SDA/PCINT5 • DI: Three-wire mode Universal Serial Interface Data input. Three-wire mode does not override normal port functions, so pin must be configured as an input. SDA: Two-wire mode Serial Interface Data. • PCINT5: Pin Change Interrupt Source 5.
ATtiny2313A/4313 Table 10-6. Overriding Signals for Alternate Functions in PB7..
10.2.3 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 10-8.. Table 10-8.
ATtiny2313A/4313 • Port D, Bit 4 – T0/PCINT15 • T0: Timer/Counter0 External Counter Clock input is enabled by setting (one) the bits CS02 and CS01 in the Timer/Counter0 Control Register (TCCR0). • PCINT15: Pin Change Interrupt Source 15. The PD4 pin can serve as an external interrupt source for pin change interrupt 2. • Port D, Bit 5 – OC0B/T1/PCINT16 • OC0B: Output Compare Match B output: The PD5 pin can serve as an external output for the Timer/Counter0 Output Compare B.
Table 10-10. Overriding Signals for Alternate Functions in PD3..PD0 10.3 10.3.
ATtiny2313A/4313 10.3.4 10.3.5 PINA – Port A Input Pins Address Bit 7 6 5 4 3 2 1 0 0x19 (0x39) – – – – – PINA2 PINA1 PINA0 Read/Write R R R R R R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A PORTB – Port B Data Register Bit 10.3.
11. 8-bit Timer/Counter0 with PWM 11.1 Features • • • • • • • 11.2 Two Independent Output Compare Units Double Buffered Output Compare Registers Clear Timer on Compare Match (Auto Reload) Glitch Free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B) Overview Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support.
ATtiny2313A/4313 uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0). The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B).
Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0).
ATtiny2313A/4313 Figure 11-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes. Be aware that the COM0x1:0 bits are not double buffered together with the compare value.
ATtiny2313A/4313 11.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Figure 11-3 on page 73. For fast PWM mode, refer to Table 10-6 on page 65, and for phase correct PWM refer to Table 10-7 on page 65.
Figure 11-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATtiny2313A/4313 PWM mode is shown in Figure 11-4. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0. Figure 11-6.
feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 11.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5.
ATtiny2313A/4313 one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 10-7 on page 65). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output.
Figure 11-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 11-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 11-10.
ATtiny2313A/4313 11.9 11.9.1 Register Description TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x30 (0x50) COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior.
Table 11-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 11-4. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. 1 1 Set OC0A on Compare Match when up-counting.
ATtiny2313A/4313 Table 11-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Compare Output Mode, Phase Correct PWM Mode(1) Table 11-7. COM0B1 COM0B0 0 0 Normal port operation, OCR0B disconnected. 0 1 Reserved 1 0 Clear ORC0B on Compare Match when up-counting. Set OCR0B on Compare Match when down-counting. 1 1 Set OCR0B on Compare Match when up-counting. Clear OCR0B on Compare Match when down-counting. Note: Description 1.
11.9.2 TCCR0B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 0x33 (0x53) FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode.
ATtiny2313A/4313 Table 11-9. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge.
11.9.6 TIMSK – Timer/Counter Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 0x39 (0x59) TOIE1 OCIE1A OCIE1B – ICIE1 OCIE0B TOIE0 OCIE0A Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK • Bit 4 – Res: Reserved Bit This bit is reserved bit in the ATtiny2313A/4313 and will always read as zero.
ATtiny2313A/4313 The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 11-8, “Waveform Generation Mode Bit Description” on page 83. • Bit 0 – OCF0A: Output Compare Flag 0 A The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Output Compare Register0 A. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag.
12. 16-bit Timer/Counter1 12.1 Features • • • • • • • • • • • 12.2 True 16-bit Design (i.e.
ATtiny2313A/4313 Most register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on. 12.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all 16-bit registers.
12.2.3 Compatibility The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version regarding: • All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers. • Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers. • Interrupt Vectors.
ATtiny2313A/4313 clkT1 Timer/Counter clock. TOP Signalize that TCNT1 has reached maximum value. BOTTOM Signalize that TCNT1 has reached minimum value (zero). The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) containing the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. The TCNT1H Register can only be indirectly accessed by the CPU.
Figure 12-3. Input Capture Unit Block Diagram DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) WRITE ICRnL (8-bit) TCNTnH (8-bit) ICRn (16-bit Register) ACO* Analog Comparator ACIC* TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Canceler Edge Detector ICFn (Int.Req.
ATtiny2313A/4313 Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the T1 pin (Figure 13-1 on page 117). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles.
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform Generator. Figure 12-4 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B).
ATtiny2313A/4313 For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 106. 12.6.1 Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC1x) bit.
Figure 12-5. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
ATtiny2313A/4313 mode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM1x1:0 bits control whether the output should be set, cleared or toggle at a compare match (See “Compare Match Output Unit” on page 95.) For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 104.
Figure 12-6. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATtiny2313A/4313 The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).
The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 flag is set.
ATtiny2313A/4313 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: log ( TOP + 1 ) R PCPWM = ----------------------------------log ( 2 ) In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11).
implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running.
ATtiny2313A/4313 In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 12-9 on page 103.
an inverted PWM output can be generated by setting the COM1x1:0 to three (See Table 12-4 on page 111). The actual OC1Fx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCF1x). The PWM waveform is generated by setting (or clearing) the OCF1x Register at the compare match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OCF1x Register at compare match between OCR1x and TCNT1 when the counter decrements.
ATtiny2313A/4313 Figure 12-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 12-12 on page 105 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
Figure 12-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value 12.10 Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus.
ATtiny2313A/4313 the OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access. Assembly Code Examples(1) ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... C Code Examples(1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1; ... Note: 1. See “Code Examples” on page 6.
The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATtiny2313A/4313 The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
12.11 Register Description 12.11.1 TCCR1A – Timer/Counter1 Control Register A Bit 7 6 5 4 3 2 1 0 0x2F (0x4F) COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1A • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respectively) behavior.
ATtiny2313A/4313 Table 12-4 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 12-4. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13=0: Normal port operation, OC1A/OC1B disconnected. WGM13=1: Toggle OC1A on Compare Match, OC1B reserved. 1 0 Clear OC1A/OC1B on Compare Match when upcounting.
Waveform Generation Mode Bit Description(1) Table 12-5.
ATtiny2313A/4313 When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. • Bit 4:3 – WGM13:2: Waveform Generation Mode See TCCR1A Register description.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. 12.11.
ATtiny2313A/4313 The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP).
• Bit 6 – OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A flag. OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
ATtiny2313A/4313 13. Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 13.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle.
ATtiny2313A/4313 14. USART 14.1 Features • • • • • • • • • • • • 14.
The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units. The Clock Generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only used by synchronous transfer mode.
ATtiny2313A/4313 Figure 14-2. Clock Generation Logic, Block Diagram UBRR U2X fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 0 1 0 OSC DDR_XCK xcki XCK Pin Sync Register Edge Detector xcko DDR_XCK 1 0 UMSEL 1 UCPOL txclk 1 0 rxclk Signal description: 14.3.1 txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK pin (Internal Signal).
Table 14-1.
ATtiny2313A/4313 14.3.4 Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. Figure 14-3. Synchronous Mode XCK Timing.
(n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter.
ATtiny2313A/4313 The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers.
14.6.1 Sending Frames with 5 to 8 Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDR I/O location. The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new frame.
ATtiny2313A/4313 14.6.2 Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written to UDR. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
contains data to be transmitted that has not yet been moved into the Shift Register. For compatibility with future devices, always write this bit to zero when writing the UCSRA Register. When the Data Register Empty Interrupt Enable (UDRIE) bit in UCSRB is written to one, the USART Data Register Empty Interrupt will be executed as long as UDRE is set (provided that global interrupts are enabled). UDRE is cleared by writing UDR.
ATtiny2313A/4313 14.7 Data Reception – The USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the Receiver’s serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done.
change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR and UPE bits, which all are stored in the FIFO, will change. The following code example shows a simple USART receive function that handles both nine bit characters and the status bits.
ATtiny2313A/4313 The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. 14.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXC) flag indicates if there are unread data present in the receive buffer.
Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPE) flag can then be read by software to check if the frame had a Parity Error. The UPE bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPM1 = 1).
ATtiny2313A/4313 the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the Double Speed mode (U2X = 1) of operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity). Figure 14-5.
Figure 14-7 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. Figure 14-7. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample 1 (U2X = 0) 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample 1 (U2X = 1) 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FE) flag will be set.
ATtiny2313A/4313 Table 14-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11/-5.19 ± 2.0 8 95.36 104.58 +4.58/-4.54 ± 2.0 9 95.81 104.14 +4.14/-4.19 ± 1.5 10 96.17 103.78 +3.78/-3.83 ± 1.5 Table 14-3.
the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed.
ATtiny2313A/4313 For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver. The transmit buffer can only be written when the UDRE flag in the UCSRA Register is set. Data written to UDR when the UDRE flag is not set, will be ignored by the USART Transmitter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will load the data into the Transmit Shift Register when the Shift Register is empty.
• Bit 2 – UPE: USART Parity Error This bit is set if the next character in the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA. • Bit 1 – U2X: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation.
ATtiny2313A/4313 • Bit 2 – UCSZ2: Character Size The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits (Character SiZe) in a frame the Receiver and Transmitter use. • Bit 1 – RXB8: Receive Data Bit 8 RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDR.
• Bit 3 – USBS: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 14-6. USBS Bit Settings USBS Stop Bit(s) 0 1-bit 1 2-bit • Bit 2:1 – UCSZ1:0: Character Size The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Character SiZe) in a frame the Receiver and Transmitter use. See Table 14-7. Table 14-7.
ATtiny2313A/4313 • Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRH is written. • Bit 11:0 – UBRR11:0: USART Baud Rate Register This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four most significant bits, and the UBRRL contains the eight least significant bits of the USART baud rate.
Table 14-10. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.
ATtiny2313A/4313 Table 14-11. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000 MHz fosc = 14.7456 MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.
Table 14-12. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000 MHz Baud Rate (bps) UBRR U2X = 1 Error UBRR Error 2400 416 -0.1% 832 0.0% 4800 207 0.2% 416 -0.1% 9600 103 0.2% 207 0.2% 14.4k 68 0.6% 138 -0.1% 19.2k 51 0.2% 103 0.2% 28.8k 34 -0.8% 68 0.6% 38.4k 25 0.2% 51 0.2% 57.6k 16 2.1% 34 -0.8% 76.8k 12 0.2% 25 0.2% 115.2k 8 -3.5% 16 2.1% 230.4k 3 8.5% 8 -3.5% 250k 3 0.0% 7 0.0% 0.5M 1 0.
ATtiny2313A/4313 15. USART in SPI Mode 15.1 Features • • • • • • • • 15.
Table 15-1. Equations for Calculating Baud Rate Register Setting Operating Mode Synchronous Master mode Note: 15.4 Equation for Calculating Baud Rate(1) Equation for Calculating UBRRn Value f OSC BAUD = ----------------------------------2 ( UBRR + 1 ) f OSC UBRR = -------------------- – 1 2BAUD 1.
ATtiny2313A/4313 15.5 Frame Formats A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM mode has two valid frame formats: • 8-bit data with MSB first • 8-bit data with LSB first A frame starts with the least or most significant data bit. Then the next data bits, up to a total of eight, are succeeding, ending with the most or least significant bit accordingly.
baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. Assembly Code Example(1) USART_Init: clr r18 out UBRRH,r18 out UBRRL,r18 ; Setting the XCK port pin as output, enables master mode. sbi XCK_DDR, XCK ; Set MSPI mode of operation and SPI data mode 0. ldi r18, (1<
ATtiny2313A/4313 15.6 Data Transfer Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXEN bit in the UCSRB register is set to one. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden and given the function as the Transmitter's serial output. Enabling the receiver is optional and is done by setting the RXEN bit in the UCSRB register to one.
Assembly Code Example(1) USART_MSPIM_Transfer: ; Wait for empty transmit buffer sbis UCSRA, UDRE rjmp USART_MSPIM_Transfer ; Put data (r16) into buffer, sends the data out UDR,r16 ; Wait for data to be received USART_MSPIM_Wait_RXC: sbis UCSRA, RXC rjmp USART_MSPIM_Wait_RXC ; Get and return received data from buffer in r16, UDR ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<
ATtiny2313A/4313 15.7 AVR USART MSPIM vs. AVR SPI The USART in MSPIM mode is fully compatible with the AVR SPI regarding: • Master mode timing diagram. • The UCPOL bit functionality is identical to the SPI CPOL bit. • The UCPHA bit functionality is identical to the SPI CPHA bit. • The UDORD bit functionality is identical to the SPI DORD bit. However, since the USART in MSPIM mode reuses the USART resources, the use of the USART in MSPIM mode is somewhat different compared to the SPI.
15.8 Register Description The following section describes the registers used for SPI operation using the USART. 15.8.1 UDR – USART MSPIM I/O Data Register The function and bit description of the USART data register (UDR) in MSPI mode is identical to normal USART operation. See “UDR – USART I/O Data Register” on page 136. 15.8.
ATtiny2313A/4313 • Bit 6 – TXCIE: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXC Flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXC bit in UCSRA is set. • Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDRE Flag.
• Bit 5:3 – Reserved Bits in MSPI mode When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written to zero when UCSRC is written. • Bit 2 – UDORD: Data Order When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is transmitted first. Refer to the Frame Formats section page 4 for details.
ATtiny2313A/4313 16. USI – Universal Serial Interface 16.1 Features • • • • • • 16.2 Two-wire Synchronous Data Transfer (Master or Slave) Three-wire Synchronous Data Transfer (Master or Slave) Data Received Interrupt Wakeup from Idle Mode In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode Two-wire Start Condition Detector with Interrupt Capability Overview The Universal Serial Interface (USI), provides the basic hardware resources needed for serial communication.
of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration. The 4-bit counter can be both read and written via the data bus, and it can generate an overflow interrupt. Both the USI Data Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete.
ATtiny2313A/4313 Figure 16-3. Three-wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The three-wire mode timing is shown in Figure 16-3 At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes.
SPITransfer_loop: out USICR,r17 in r16, USISR sbrs r16, USIOIF rjmp SPITransfer_loop in r16,USIDR ret The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and USCK pins have been enabled as outputs in DDRA. The value stored in register r16 prior to the function is called is transferred to the slave device, and when the transfer is completed the data received from the slave is stored back into the register r16.
ATtiny2313A/4313 16.3.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ldi r16,(1<
Figure 16-4. Two-wire Mode Operation, Simplified Diagram VCC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL HOLD SCL Two-wire Clock Control Unit SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL PORTxn MASTER The data direction is not given by the physical layer. A protocol, like the one used by the TWIbus, must be implemented to control the data flow. Figure 16-5.
ATtiny2313A/4313 3. The master set the first bit to be transferred and releases the SCL line (C). The slave samples the data and shifts it into the USI Data Register at the positive edge of the SCL clock. 4. After eight bits containing slave address and data direction (read or write) have been transferred, the slave counter overflows and the SCL line is forced low (D). If the slave is not the one the master has addressed, it releases the SCL line and waits for a new start condition. 5.
16.4 Alternative USI Usage The flexible design of the USI allows it to be used for other tasks when serial communication is not needed. Below are some examples. 16.4.1 Half-Duplex Asynchronous Data Transfer Using the USI Data Register in three-wire mode it is possible to implement a more compact and higher performance UART than by software, only. 16.4.2 4-Bit Counter The 4-bit counter can be used as a stand-alone counter with overflow interrupt.
ATtiny2313A/4313 Data Register can therefore be clocked externally and data input sampled, even when outputs are disabled. Table 16-1. Relationship between USIWM1:0 and USI Operation USIWM1 USIWM0 0 0 Outputs, clock hold, and start detector disabled. Port pins operate as normal. 1 Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORTA register. However, the corresponding DDRA bit still controls the data direction.
Table 16-2 shows the relationship between the USICS1:0 and USICLK setting and clock source used for the USI Data Register and the 4-bit counter. Table 16-2.
ATtiny2313A/4313 If USISIE bit in USICR and the Global Interrupt Enable Flag are set, an interrupt will be generated when this flag is set. The flag will only be cleared by writing a logical one to the USISIF bit. Clearing this bit will release the start detection hold of USCL in two-wire mode. A start condition interrupt will wakeup the processor from all sleep modes. • Bit 6 – USIOIF: Counter Overflow Interrupt Flag This flag is set (one) when the 4-bit counter overflows (i.e.
Note that even when no wire mode is selected (USIWM1:0 = 0) both the external data input (DI/SDA) and the external clock input (USCK/SCL) can still be used by the USI Data Register. The output pin (DO or SDA, depending on the wire mode) is connected via the output latch to the most significant bit (bit 7) of the USI Data Register. The output latch ensures that data input is sampled and data output is changed on opposite clock edges.
ATtiny2313A/4313 17. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
• Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
ATtiny2313A/4313 18. debugWIRE On-chip Debug System 18.1 Features • • • • • • • • • • 18.
• Pull-Up resistor on the dW/(RESET) line must be larger than 10k. However, the pull-up resistor is optional. • Connecting the RESET pin directly to VCC will not work. • Capacitors inserted on the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. 18.4 Software Break Points debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a Break Point in AVR Studio® will insert a BREAK instruction in the Program memory.
ATtiny2313A/4313 18.6 Register Description The following section describes the registers used with the debugWire. 18.6.1 DWDR – debugWire Data Register Bit 7 6 5 4 3 2 1 0 DWDR[7:0] DWDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The DWDR Register provides a communication channel from the running program in the MCU to the debugger.
19. Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The SPM instruction is disabled by default but it can be enabled by programming the SELFPRGEN fuse (to “0”). The Program memory is updated in a page by page fashion.
ATtiny2313A/4313 19.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. Note: 19.4 The CPU is halted during the Page Write operation. Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands.
19.5 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. 19.
ATtiny2313A/4313 To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and repeat the procedure above. If successful, the contents of the destination register are as follows. Bit 7 6 5 4 3 2 1 0 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 Refer to Table 20-4 on page 179 for detailed description and mapping of the Fuse High Byte. To read the Fuse Extended Byte (FEB), replace the address in the Z-pointer with 0x0002 and repeat the previous procedure.
19.7 Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly.
ATtiny2313A/4313 imprint table into the destination register. See “Device Signature Imprint Table” on page 180 for details. • Bit 4 – CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost.
20. Memory Programming This section describes the different methods for programming ATtiny2313A/4313 memories. 20.1 Program And Data Memory Lock Bits The ATtiny2313A/4313 provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 20-2. The Lock bits can only be erased to “1” with the Chip Erase command. Program memory can be read out via the debugWIRE interface when the DWEN fuse is programmed, even if lock bits are set.
ATtiny2313A/4313 20.2 Fuse Bits The ATtiny2313A/4313 has three Fuse bytes. Table 20-3, Table 20-4 and Table 20-5 describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 20-3.
Table 20-5. Fuse Low Byte Fuse Low Byte Bit No Description Default Value CKDIV8 7 Divide clock by 8 0 (programmed) CKOUT 6 Output Clock on CKOUT pin 1 (unprogrammed) SUT1 5 Select start-up time 1 (unprogrammed)(1) SUT0 4 Select start-up time 0 (programmed)(1) CKSEL3 3 Select Clock source 0 (programmed)(2) CKSEL2 2 Select Clock source 1 (unprogrammed)(2) CKSEL1 1 Select Clock source 0 (programmed)(2) CKSEL0 0 Select Clock source 0 (programmed)(2) Notes: 1.
ATtiny2313A/4313 Notes: 1. See section “Signature Bytes” for more information. 2. See section “Calibration Byte” for more information. 20.3.1 Calibration Byte The signature area of the ATtiny2313A/4313 contains two bytes of calibration data for the internal oscillator. The calibration data in the high byte of address 0x00 is for use with the oscillator set to 8.0 MHz operation. During reset, this byte is automatically written into the OSCCAL register to ensure correct frequency of the oscillator.
20.5 Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATtiny2313A/4313. Pulses are assumed to be at least 250 ns unless otherwise noted. 20.5.1 Signal Names In this section, some pins of the ATtiny2313A/4313 are referenced by signal names describing their functionality during parallel programming, see Figure 20-1 and Table 20-9 on page 182.
ATtiny2313A/4313 Table 20-10. Pin Values Used to Enter Programming Mode Pin Symbol Value XA1 Prog_enable[3] 0 XA0 Prog_enable[2] 0 BS1 Prog_enable[1] 0 WR Prog_enable[0] 0 Table 20-11. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1).
4. Wait 20 - 60 µs, and apply 11.5 - 12.5V to RESET. 5. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has been applied to ensure the Prog_enable Signature has been latched. 6. Wait at least 300 µs before giving any parallel programming commands. 7. Exit Programming mode by power the device down or by bringing RESET pin to 0V. If the rise time of the VCC is unable to fulfill the requirements listed above, the following alternative algorithm can be used. 1.
ATtiny2313A/4313 grammed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4. Give XTAL1 a positive pulse. This loads the command. B. Load Address Low byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “0”. This selects low address. 3. Set DATA = Address low byte (0x00 - 0xFF).
3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 20-2. Addressing the Flash Which is Organized in Pages(1) PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: 1. PCPAGE and PCWORD are listed in Table 20-7 on page 181. Figure 20-3. Programming the Flash Waveforms(1) F DATA A B 0x10 ADDR.
ATtiny2313A/4313 3. B: Load Address Low Byte (0x00 - 0xFF). 4. C: Load Data (0x00 - 0xFF). J: Repeat 3 through 4 until the entire buffer is filled. K: Program EEPROM page 1. Set BS1 to “0”. 2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low. 3. Wait until to RDY/BSY goes high before programming the next page (See Figure 20-4 for signal waveforms). Figure 20-4. Programming the EEPROM Waveforms K DATA A G 0x11 ADDR. HIGH B ADDR. LOW C DATA E XX B ADDR.
20.6.8 Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (refer to “Programming the Flash” on page 184 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high. 20.6.
ATtiny2313A/4313 20.6.11 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 184 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed (LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any External Programming mode. 3. Give WR a negative pulse and wait for RDY/BSY to go high.
20.6.14 Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to “Programming the Flash” on page 184 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte, 0x00. 3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA. 4. Set OE to “1”. 20.7 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND.
ATtiny2313A/4313 20.8 Serial Programming Pin Mapping Table 20-13. Pin Mapping Serial Programming 20.8.1 Symbol Pins I/O Description MOSI PB5 I Serial Data in MISO PB6 O Serial Data out SCK PB7 I Serial Clock Serial Programming Algorithm When writing serial data to the ATtiny2313A/4313, data is clocked on the rising edge of SCK. When reading data from the ATtiny2313A/4313, data is clocked on the falling edge of SCK. See Figure 20.8.2, Figure 21-6 and Table 21-8 for timing details.
next page (See Table 20-14 on page 192). In a chip erased device, no 0xFF in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off. Table 20-14.
ATtiny2313A/4313 20.8.2 Serial Programming Instruction Set Table 20-15. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Operation Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.
Table 20-15. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Read Extended Fuse Bits 0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” = programmed, “1” = unprogrammed. Read Calibration Byte 0011 1000 000x xxxx 0000 000b oooo oooo Read Calibration Byte at address b. Poll RDY/BSY 1111 0000 0000 0000 xxxx xxxx xxxx xxxo If o = “1”, a programming operation is still busy.
ATtiny2313A/4313 21. Electrical Characteristics 21.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating Voltage ............................................ 6.
TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Typ. Max. Units (7) Min. 0.2 0.55 mA (7) 1.3 2.5 mA (7) Active 8MHz, VCC = 5V 3.9 7 mA Idle 1MHz, VCC = 2V(7) 0.03 0.15 mA Idle 4MHz, VCC = 3V(7) 0.25 0.6 mA 1 2 mA 4 10 µA < 0.15 2 µA Active 1MHz, VCC = 2V Active 4MHz, VCC = 3V Power Supply Current ICC (7) Idle 8MHz, VCC = 5V (8) Power-down mode Notes: WDT enabled, VCC = 3V WDT disabled, VCC = 3V(8) 1.
ATtiny2313A/4313 21.4 Clock Characteristics 21.4.1 Calibrated Internal RC Oscillator Accuracy It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics can be found in Figure 22-46 on page 226, and Figure 22-47 on page 227. Table 21-1.
21.5 System and Reset Characteristics Table 21-3. Symbol Reset, Brown-out, and Internal Voltage Characteristics Parameter VRST RESET Pin Threshold Voltage tRST Minimum pulse width on RESET Pin (1)(2) Condition Min Typ 0.2 VCC VCC = 1.8 - 5.5V Max Units 0.8VCC V 2.5 µs VHYST Brown-out Detector Hysteresis (2) 50 mV tBOD Min Pulse Width on Brown-out Reset (2) 2 µs VBG Internal bandgap reference voltage VCC = 2.
ATtiny2313A/4313 21.6 Analog Comparator Characteristics Table 21-6. Analog Comparator Characteristics, TA = -40°C - 85°C Symbol Parameter Condition VACIO Input Offset Voltage VCC = 5V, VIN = VCC / 2 IACLK Input Leakage Current VCC = 5V, VIN = VCC / 2 Analog Propagation Delay (from saturation to slight overdrive) VCC = 2.7V 750 VCC = 4.0V 500 Analog Propagation Delay (large step change) VCC = 2.7V 100 VCC = 4.0V 75 Digital Propagation Delay VCC = 1.8V - 5.
21.7 Parallel Programming Characteristics Table 21-7. Symbol Parameter Min VPP Programming Enable Voltage 11.
ATtiny2313A/4313 Figure 21-3. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 tDVXH tXLDX Data & Contol (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 21-4.
21.8 Serial Programming Characteristics Figure 21-6. Serial Programming Timing MOSI SCK tSLSH tSHOX tOVSH tSHSL MISO Figure 21-7. Serial Programming Waveform SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Table 21-8. Symbol Parameter 1/tCLCL Oscillator Frequency (ATtiny2313A/4313) Oscillator Period (ATtiny2313A/4313) tCLCL Min 0 Typ Max Units 4 MHz 250 ns Oscillator Frequency (ATtiny2313A/4313, VCC = 4.5V - 5.
ATtiny2313A/4313 22. Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing.
22.2 22.2.1 ATtiny2313A Current Consumption in Active Mode Figure 22-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY (ATtiny2313A) (PRR=0xFF) 1 5.5 V 0,8 5.0 V 4.5 V ICC (mA) 0,6 3.3 V 0,4 2.7 V 1.8 V 0,2 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 22-2. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY (ATtiny2313A) (PRR=0xFF) 10 5.5V 5.0V 8 4.5V ICC (mA) 6 4 3.3V 2.
ATtiny2313A/4313 Figure 22-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. VCC (ATtiny2313A) INTERNAL RC OSCILLATOR, 8 MHz 5 85 °C 25 °C -40 °C 4 ICC (mA) 3 2 1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs.
Figure 22-5. Active Supply Current vs. VCC (Internal RC Oscillator, 128 KHz) ACTIVE SUPPLY CURRENT vs. VCC (ATtiny2313A) INTERNAL RC OSCILLATOR, 128 KHz 0,12 -40 °C 25 °C 85 °C 0,1 ICC (mA) 0,08 0,06 0,04 0,02 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 22.2.2 Current Consumption in Idle Mode Figure 22-6. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY (ATtiny2313A) (PRR=0xFF) 0,16 5.5 V 0,14 5.0 V 0,12 4.5 V 0,1 ICC (mA) 4.0 V 0,08 3.
ATtiny2313A/4313 Figure 22-7. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY (ATtiny2313A) (PRR=0xFF) 3 5.5 V 2,5 5.0 V 4.5 V ICC (mA) 2 1,5 4.0 V 1 3.3 V 2.7 V 0,5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 22-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs.
Figure 22-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs. VCC (ATtiny2313A) INTERNAL RC OSCILLATOR, 1 MHz 0,3 85 °C 0,25 25 °C -40 °C ICC (mA) 0,2 0,15 0,1 0,05 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 KHz) IDLE SUPPLY CURRENT vs.
ATtiny2313A/4313 22.2.3 Current Consumption in Power-down Mode Figure 22-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. VCC (ATtiny2313A) WATCHDOG TIMER DISABLED 0,5 85 °C 0,4 ICC (uA) 0,3 0,2 25 °C 0,1 -40 °C 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs.
22.2.4 Current Consumption in Reset Figure 22-13. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. VCC (ATtiny2313A) EXCLUDING CURRENT THROUGH THE RESET PULLUP 0,14 0,12 5.5 V 5.0 V 0,1 4.5 V ICC (mA) 0,08 4.0 V 0,06 3.3 V 2.7 V 0,04 1.8 V 0,02 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 22-14. Reset Supply Current vs.
ATtiny2313A/4313 22.2.5 Current Consumption of Peripheral Units Figure 22-15. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC (ATtiny2313A) BOD level = 1.8V 35 30 25 85 °C 25 °C ICC (uA) 20 -40 °C 15 10 5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-16. Programming Current vs. VCC (ATtiny2313A) PROGRAMMING CURRENT vs.
22.2.6 Pull-up Resistors Figure 22-17. Pull-up Resistor Current vs. Input Voltage (I/O Pin, VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE (ATtiny2313A) 60 50 IOP (uA) 40 30 20 10 25 °C 85 °C -40 °C 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VOP (V) Figure 22-18. Pull-up Resistor Current vs. Input Voltage (I/O Pin, VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs.
ATtiny2313A/4313 Figure 22-19. Pull-up Resistor Current vs. Input Voltage (I/O Pin, VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE (ATtiny2313A) 160 140 120 IOP (uA) 100 80 60 40 20 25 °C 85 °C -40 °C 0 0 2 1 3 4 5 6 VOP (V) Figure 22-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) RESET PULL-UP RESISTOR CURRENT vs.
Figure 22-21. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE (ATtiny2313A) 60 50 IRESET (uA) 40 30 20 10 25 °C -40 °C 85 °C 0 0 0,5 1 1, 5 2 2, 5 3 VRESET (V) Figure 22-22. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs.
ATtiny2313A/4313 22.2.7 Output Driver Strength Figure 22-23. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT (ATtiny2313A) Vcc = 1.8V 0,4 85 °C 0,35 0,3 25 °C 0,25 VOL (V) -40 °C 0,2 0,15 0,1 0,05 0 0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5 IOL (mA) Figure 22-24. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 3V) I/O PIN OUTPUT VOLTAGE vs.
Figure 22-25. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT (ATtiny2313A) Vcc = 5V 0,6 85 °C 0,5 25 °C VOL (V) 0,4 -40 °C 0,3 0,2 0,1 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 22-26. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT (ATtiny2313A) Vcc = 1.
ATtiny2313A/4313 Figure 22-27. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT (ATtiny2313A) Vcc = 3V 3,1 3 VOH (V) 2,9 2,8 -40 °C 2,7 25 °C 2,6 85 °C 2,5 0 2 4 6 8 10 IOH (mA) Figure 22-28. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 5V) I/O PIN OUTPUT VOLTAGE vs.
Figure 22-29. VOL: Output Voltage vs. Sink Current (Reset Pin as I/O, T = 25°C) RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT (ATtiny2313A) 1 3.0 V 1.8 V 0,9 0,8 0,7 5.0 V VOL (V) 0,6 0,5 0,4 0,3 0,2 0,1 0 0 1 2 3 4 IOL (mA) Figure 22-30. VOH: Output Voltage vs. Source Current (Reset Pin as I/O, T = 25°C) RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT (ATtiny2313A) 5 4 5.0 V VOH (V) 3 2 3.0 V 1 1.
ATtiny2313A/4313 22.2.8 Input Thresholds and Hysteresis (for I/O Ports) Figure 22-31. VIH: Input Threshold Voltage vs. VCC (I/O Pin Read as ‘1’) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC (ATtiny2313A) VIH, IO PIN READ AS '1' 3,5 85 °C 25 °C -40 °C 3 2,5 Threshold (V) 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-32. VIL: Input Threshold Voltage vs. VCC (I/O Pin, Read as ‘0’) I/O PIN INPUT THRESHOLD VOLTAGE vs.
Figure 22-33. VIH-VIL: Input Hysteresis vs. VCC (I/O Pin) I/O PIN INPUT HYSTERESIS vs. VCC (ATtiny2313A) 0,6 -40 °C 0,5 25 °C Input Hysteresis (mV) 0,4 85 °C 0,3 0,2 0,1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-34. VIH: Input Threshold Voltage vs. VCC (Reset Pin as I/O, Read as ‘1’) RESET PIN AS I/O THRESHOLD VOLTAGE vs.
ATtiny2313A/4313 Figure 22-35. VIL: Input Threshold Voltage vs. VCC (Reset Pin as I/O, Read as ‘0’) RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC (ATtiny2313A) VIL, RESET READ AS '0' 2,5 2 Threshold (V) 1,5 1 85 °C 25 °C -40 °C 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 5 5,5 VCC (V) Figure 22-36. VIH-VIL: Input Hysteresis vs. VCC (Reset Pin as I/O) RESET PIN AS IO, INPUT HYSTERESIS vs.
22.2.9 BOD, Bandgap and Reset Figure 22-37. BOD Thresholds vs. Temperature (BOD Level is 4.3V) BOD THRESHOLDS vs. TEMPERATURE (BOD Level set to 4.3V) (ATtiny2313A) BODLEVEL = 4.3V 4,36 VCC RISING 4,34 4,32 Threshold (V) 4,3 4,28 VCC FALLING 4,26 4,24 4,22 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C) Figure 22-38. BOD Thresholds vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE (BOD Level set to 2.7V) (ATtiny2313A) BODLEVEL = 2.
ATtiny2313A/4313 Figure 22-39. BOD Thresholds vs. Temperature (BOD Level is 1.8V) BOD THRESHOLDS vs. TEMPERATURE (BOD Level set to 1.8V) (ATtiny2313A) BODLEVEL = 1.8V 1,84 1,83 VCC RISING Threshold (V) 1,82 1,81 VCC FALLING 1,8 1,79 1,78 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 22-40. Bandgap Voltage vs. Supply Voltage BANDGAP VOLTAGE vs.
Figure 22-41. Bandgap Voltage vs. Temperature BANDGAP VOLTAGE vs. TEMP (ATtiny2313A) (Vcc=5V) 1,16 1,14 Bandgap Voltage (V) 1,12 CALIBRATED 1,1 1,08 1,06 1,04 1,02 1 -40 -20 0 20 40 60 80 100 Temperature Figure 22-42. VIH: Input Threshold Voltage vs. VCC (Reset Pin, Read as ‘1’) RESET INPUT THRESHOLD VOLTAGE vs.
ATtiny2313A/4313 Figure 22-43. VIL: Input Threshold Voltage vs. VCC (Reset Pin, Read as ‘0’) RESET INPUT THRESHOLD VOLTAGE vs. VCC (ATtiny2313A) VIL, IO PIN READ AS '0' 2,5 85 °C 25 °C -40 °C 2 Threshold (V) 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 5 5,5 VCC (V) Figure 22-44. VIH-VIL: Input Hysteresis vs. VCC (Reset Pin) RESET PIN INPUT HYSTERESIS vs.
Figure 22-45. Minimum Reset Pulse Width vs. VCC MINIMUM RESET PULSE WIDTH vs. VCC (ATtiny2313A) 2000 1800 1600 1400 Pulsewidth (ns) 1200 1000 800 600 400 85 °C 25 °C -40 °C 200 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 22.2.10 Internal Oscillator Speed Figure 22-46. Calibrated 8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8.0MHz RC OSCILLATOR FREQUENCY vs.
ATtiny2313A/4313 Figure 22-47. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8.0MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE (ATtiny2313A) 9 1.8 V 3.0 V 5.0 V FRC (MHz) 8,5 8 7,5 7 -40 -20 0 20 40 60 80 100 Temperature Figure 22-48. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8.0MHz RC OSCILLATOR FREQUENCY vs.
22.3 22.3.1 ATtiny4313 Current Consumption in Active Mode Figure 22-49. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY (ATtiny4313) (PRR=0xFF) 1 5.5 V 0,8 5.0 V 4.5 V ICC (mA) 0,6 3.3 V 0,4 2.7 V 0,2 1.8 V 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 22-50. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY (ATtiny4313) (PRR=0xFF) 10 5.5V 5.0V 8 4.5V ICC (mA) 6 4 3.3V 2.
ATtiny2313A/4313 Figure 22-51. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. VCC (ATtiny4313) INTERNAL RC OSCILLATOR, 8 MHz 5 85 °C 25 °C -40 °C 4 ICC (mA) 3 2 1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-52. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs.
Figure 22-53. Active Supply Current vs. VCC (Internal RC Oscillator, 128 KHz) ACTIVE SUPPLY CURRENT vs. VCC (ATtiny4313) INTERNAL RC OSCILLATOR, 128 KHz 0,12 -40 °C 25 °C 85 °C 0,1 ICC (mA) 0,08 0,06 0,04 0,02 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 22.3.2 Current Consumption in Idle Mode Figure 22-54. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY (ATtiny4313) (PRR=0xFF) 0,16 0,14 5.5 V 0,12 5.0 V 4.5 V 0,1 ICC (mA) 4.0 V 0,08 3.
ATtiny2313A/4313 Figure 22-55. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY (ATtiny4313) (PRR=0xFF) 3 5.5 V 2,5 5.0 V 4.5 V ICC (mA) 2 1,5 4.0 V 1 3.3 V 2.7 V 0,5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 22-56. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs.
Figure 22-57. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs. VCC (ATtiny4313) INTERNAL RC OSCILLATOR, 1 MHz 0,4 0,3 ICC (mA) 85 °C 25 °C -40 °C 0,2 0,1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-58. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 KHz) IDLE SUPPLY CURRENT vs.
ATtiny2313A/4313 22.3.3 Current Consumption in Power-down Mode Figure 22-59. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. VCC (ATtiny4313) WATCHDOG TIMER DISABLED 0,6 85 °C 0,5 ICC (uA) 0,4 0,3 0,2 25 °C 0,1 -40 °C 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-60. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs.
22.3.4 Current Consumption in Reset Figure 22-61. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. VCC (ATtiny4313) EXCLUDING CURRENT THROUGH THE RESET PULLUP 0,12 5.5 V 0,1 5.0 V 4.5 V 0,08 ICC (mA) 4.0 V 0,06 3.3 V 2.7 V 0,04 1.8 V 0,02 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 22-62. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs.
ATtiny2313A/4313 22.3.5 Current Consumption of Peripheral Units Figure 22-63. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC (ATtiny4313) BOD level = 1.8V 35 30 25 85 °C 25 °C -40 °C ICC (uA) 20 15 10 5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-64. Programming Current vs. VCC (ATtiny4313) PROGRAMMING CURRENT vs.
22.3.6 Pull-up Resistors Figure 22-65. Pull-up Resistor Current vs. Input Voltage (I/O Pin, VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE (ATtiny4313) 60 50 IOP (uA) 40 30 20 10 25 °C 85 °C -40 °C 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VOP (V) Figure 22-66. Pull-up Resistor Current vs. Input Voltage (I/O Pin, VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs.
ATtiny2313A/4313 Figure 22-67. Pull-up Resistor Current vs. Input Voltage (I/O Pin, VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE (ATtiny4313) 160 140 120 IOP (uA) 100 80 60 40 20 25 °C 85 °C -40 °C 0 0 1 2 3 5 4 6 VOP (V) Figure 22-68. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) RESET PULL-UP RESISTOR CURRENT vs.
Figure 22-69. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE (ATtiny4313) 60 50 IRESET (uA) 40 30 20 10 25 °C -40 °C 85 °C 0 0 0, 5 1 1,5 2 2,5 3 VRESET (V) Figure 22-70. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs.
ATtiny2313A/4313 22.3.7 Output Driver Strength Figure 22-71. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT (ATtiny4313) VCC = 1.8V 0,4 85 °C 0,35 0,3 25 °C 0,25 VOL (V) -40 °C 0,2 0,15 0,1 0,05 0 0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5 IOL (mA) Figure 22-72. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 3V) I/O PIN OUTPUT VOLTAGE vs.
Figure 22-73. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT (ATtiny4313) VCC = 5V 0,6 85 °C 0,5 25 °C -40 °C VOL (V) 0,4 0,3 0,2 0,1 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 22-74. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT (ATtiny4313) VCC = 1.
ATtiny2313A/4313 Figure 22-75. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT (ATtiny4313) VCC = 3V 3,1 3 VOH (V) 2,9 2,8 -40 °C 2,7 25 °C 2,6 85 °C 2,5 0 2 4 6 8 10 IOH (mA) Figure 22-76. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 5V) I/O PIN OUTPUT VOLTAGE vs.
Figure 22-77. VOL: Output Voltage vs. Sink Current (Reset Pin as I/O, T = 25°C) RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT (ATtiny4313) 1 3.0 V 1.8 V 0,9 0,8 0,7 5.0 V VOL (V) 0,6 0,5 0,4 0,3 0,2 0,1 0 1 0 3 2 4 IOL (mA) Figure 22-78. VOH: Output Voltage vs. Source Current (Reset Pin as I/O, T = 25°C) RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT (ATtiny4313) 5 4 VOH (V) 3 5.0V 2 3.0V 1 1.
ATtiny2313A/4313 22.3.8 Input Thresholds and Hysteresis (for I/O Ports) Figure 22-79. VIH: Input Threshold Voltage vs. VCC (I/O Pin Read as ‘1’) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC (ATtiny4313) VIH, IO PIN READ AS '1' 3,5 85 °C 25 °C -40 °C 3 2,5 Threshold (V) 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-80. VIL: Input Threshold Voltage vs. VCC (I/O Pin, Read as ‘0’) I/O PIN INPUT THRESHOLD VOLTAGE vs.
Figure 22-81. VIH-VIL: Input Hysteresis vs. VCC (I/O Pin) I/O PIN INPUT HYSTERESIS vs. VCC (ATtiny4313) 0,6 -40 °C 0,5 25 °C Input Hysteresis (mV) 0,4 85 °C 0,3 0,2 0,1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-82. VIH: Input Threshold Voltage vs. VCC (Reset Pin as I/O, Read as ‘1’) RESET PIN AS I/O THRESHOLD VOLTAGE vs.
ATtiny2313A/4313 Figure 22-83. VIL: Input Threshold Voltage vs. VCC (Reset Pin as I/O, Read as ‘0’) RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC (ATtiny4313) VIL, RESET READ AS '0' 2,5 2 Threshold (V) 1,5 1 85 °C 25 °C -40 °C 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 5 5,5 VCC (V) Figure 22-84. VIH-VIL: Input Hysteresis vs. VCC (Reset Pin as I/O) RESET PIN AS IO, INPUT HYSTERESIS vs.
22.3.9 BOD, Bandgap and Reset Figure 22-85. BOD Thresholds vs. Temperature (BOD Level is 4.3V) BOD THRESHOLDS vs. TEMPERATURE (BOD Level set to 4.3V) (ATtiny4313) BOD Level = 4.3V 4,38 4,36 VCC RISING 4,34 4,32 Threshold (V) 4,3 4,28 VCC FALLING 4,26 4,24 4,22 4,2 4,18 4,16 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C) Figure 22-86. BOD Thresholds vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE (BOD Level set to 2.7V) (ATtiny4313) BOD Level = 2.
ATtiny2313A/4313 Figure 22-87. BOD Thresholds vs. Temperature (BOD Level is 1.8V) BOD THRESHOLDS vs. TEMPERATURE (BOD Level set to 1.8V) (ATtiny4313) BOD Level = 1.8V 1,84 1,83 VCC RISING 1,82 Threshold (V) 1,81 VCC FALLING 1,8 1,79 1,78 1,77 1,76 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 22-88. Bandgap Voltage vs. Supply Voltage BANDGAP VOLTAGE vs.
Figure 22-89. Bandgap Voltage vs. Temperature BANDGAP VOLTAGE vs. TEMP (ATtiny4313) (Vcc=5V) 1,14 1,12 Bandgap Voltage (V) 1,1 CALIBRATED 1,08 1,06 1,04 1,02 1 -40 -20 0 20 40 60 80 100 Temperature Figure 22-90. VIH: Input Threshold Voltage vs. VCC (Reset Pin, Read as ‘1’) RESET INPUT THRESHOLD VOLTAGE vs.
ATtiny2313A/4313 Figure 22-91. VIL: Input Threshold Voltage vs. VCC (Reset Pin, Read as ‘0’) RESET INPUT THRESHOLD VOLTAGE vs. VCC (ATtiny4313) VIL, IO PIN READ AS '0' 2,5 85 °C 25 °C -40 °C 2 Threshold (V) 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-92. VIH-VIL: Input Hysteresis vs. VCC (Reset Pin) RESET PIN INPUT HYSTERESIS vs.
Figure 22-93. Minimum Reset Pulse Width vs. VCC MINIMUM RESET PULSE WIDTH vs. VCC (ATtiny4313) 1800 1600 1400 Pulsewidth (ns) 1200 1000 800 600 400 85 °C 25 °C -40 °C 200 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 22.3.10 Internal Oscillator Speed Figure 22-94. Calibrated 8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8.0MHz RC OSCILLATOR FREQUENCY vs.
ATtiny2313A/4313 Figure 22-95. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8.0MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE (ATtiny4313) 8,6 5.0 V 3.0 V 1.8 V 8,4 FRC (MHz) 8,2 8 7,8 7,6 7,4 -40 -20 0 20 40 60 80 100 Temperature Figure 22-96. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8.0MHz RC OSCILLATOR FREQUENCY vs.
23.
ATtiny2313A/4313 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them.
24.
ATtiny2313A/4313 Mnemonics Operands Description Operation Flags #Clocks ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..
25. Ordering Information 25.1 ATtiny2313A Speed (MHz) Power Supply 20(3) Notes: 1.8 - 5.5V Ordering Code(2) ATtiny2313A-PU ATtiny2313A-SU ATtiny2313A-MU ATtiny2313A-MMH(4)(5) Package(1) Operation Range 20P3 20S 20M1 20M2 Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
ATtiny2313A/4313 25.2 ATtiny4313 Speed (MHz) Power Supply (3) 20 Notes: 1.8 - 5.5V Ordering Code(2) ATtiny4313-PU ATtiny4313-SU ATtiny4313-MU ATtiny4313-MMH(4)(5) Package(1) Operation Range 20P3 20S 20M1 20M2 Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
26. Packaging Information 26.1 20P3 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E COMMON DIMENSIONS (Unit of Measure = mm) C eC eB Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). MIN NOM MAX A – – 5.334 A1 0.381 – – D 25.493 – 25.984 E 7.620 – 8.255 E1 6.096 – 7.112 B 0.356 – 0.559 B1 1.270 – 1.551 L 2.921 – 3.
ATtiny2313A/4313 26.
26.3 20M1 D 1 Pin 1 ID 2 SIDE VIEW E 3 TOP VIEW A2 D2 A1 A 0.08 1 2 Pin #1 Notch (0.20 R) 3 COMMON DIMENSIONS (Unit of Measure = mm) E2 b L e BOTTOM VIEW SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 – 0.01 0.05 A2 b 0.18 D D2 E2 L 0.23 0.30 4.00 BSC 2.45 2.60 2.75 4.00 BSC 2.45 e Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. NOTE 0.20 REF E Note: C 2.60 2.75 0.50 BSC 0.35 0.40 0.
ATtiny2313A/4313 26.4 20M2 D C y Pin 1 ID E SIDE VIEW TOP VIEW A1 A D2 16 17 18 19 20 COMMON DIMENSIONS (Unit of Measure = mm) C0.18 (8X) 15 Pin #1 Chamfer (C 0.3) 14 2 e E2 13 3 12 4 11 5 MIN NOM MAX A 0.75 0.80 0.85 A1 0.00 0.02 0.05 b 0.17 0.22 0.27 SYMBOL 1 C b 10 9 8 7 6 K L BOTTOM VIEW 0.3 Ref (4x) NOTE 0.152 D 2.90 3.00 3.10 D2 1.40 1.55 1.70 E 2.90 3.00 3.10 E2 1.40 1.55 1.70 e – 0.45 – L 0.35 0.40 0.45 K 0.20 – – y 0.
27. Errata The revision letters in this section refer to the revision of the corresponding ATtiny2313A/4313 device. 27.1 27.1.1 ATtiny2313A Rev. D No known errata. 27.1.2 Rev. A – C These device revisions were referred to as ATtiny2313/ATtiny2313V. 27.2 27.2.1 ATtiny4313 Rev. A No known errata.
ATtiny2313A/4313 28. Datasheet Revision History 28.1 Rev. 8246A – 11/09 1. Initial revision. Created from document 2543_t2313. 2. Updated datasheet template. 3. Added VQFN in the Pinout Figure 1-1 on page 2. 4. Added Section 7.2 “Software BOD Disable” on page 34. 5. Added Section 7.3 “Power Reduction Register” on page 34. 6. Updated Table 7-2, “Sleep Mode Select,” on page 36. 7. Added Section 7.5.3 “BODCR – Brown-Out Detector Control Register” on page 37. 8.
ATtiny2313A/4313 8246A–AVR–11/09
ATtiny2313A/4313 Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1 2 3 4 5 6 7 Pin Descriptions .................................................................................................2 Overview ................................................................................................... 4 2.
8 9 7.1 Sleep Modes ....................................................................................................33 7.2 Software BOD Disable .....................................................................................34 7.3 Power Reduction Register ...............................................................................34 7.4 Minimizing Power Consumption ......................................................................35 7.5 Register Description .......................
ATtiny2313A/4313 12.5 Input Capture Unit ...........................................................................................91 12.6 Output Compare Units .....................................................................................93 12.7 Compare Match Output Unit ............................................................................95 12.8 Modes of Operation .........................................................................................96 12.
16.2 Overview ........................................................................................................155 16.3 Functional Descriptions .................................................................................156 16.4 Alternative USI Usage ...................................................................................162 16.5 Register Description ......................................................................................162 17 Analog Comparator .................
ATtiny2313A/4313 21.2 DC Characteristics .........................................................................................195 21.3 Speed Grades ...............................................................................................196 21.4 Clock Characteristics .....................................................................................197 21.5 System and Reset Characteristics ................................................................198 21.
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