Datasheet

ATtiny2313/V

2543H–AVR–02/05

the edge detector uses sampling, the maximum frequency of an external clock it can

detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari-

ation of the system clock frequency and duty cycle caused by Oscillator source (crystal,

resonator, and capacitors) tolerances, it is recommended that maximum frequency of an

external clock source is less than f

clk_I/O

/2.5.

An external clock source can not be prescaled.

Figure 39. Prescaler for Timer/Counter0 and Timer/Counter1

(1)

Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 38.

General Timer/Counter

Control Register – GTCCR

• Bits 7..1 – Res: Reserved Bits

These bits are reserved bits in the ATtiny2313 and will always read as zero.

• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0

When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This

bit is normally cleared immediately by hardware. Note that Timer/Counter1 and

Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both

timers.

PSR10

Clear

clk

I/O

Synchronization

Bit 7 6 5 4 3 2 1 0

— – – – – – — PSR10 GTCCR

Read/Write R R R R R R R R/W

Initial Value 0 0 0 0 0 0 0 0