Datasheet

79
ATtiny2313/V
2543H–AVR–02/05
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and
the data in OCR0A – Output Compare Register0 A. OCF0A is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF0A is
cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A
(Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the
Timer/Counter0 Compare Match Interrupt is executed.