Datasheet

ATtiny2313/V

2543H–AVR–02/05

8-bit Timer/Counter

Timer/Counter Control

• Bits 7:6 – COM0A1:0: Compare Match Output A Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the

COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the

I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit cor-

responding to the OC0A pin must be set in order to enable the output driver.

When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the

WGM02:0 bit setting. Table 34 shows the COM0A1:0 bit functionality when the

WGM02:0 bits are set to a normal or CTC mode (non-PWM).

Table 35 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast

PWM mode.

Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case,

the Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWM

Mode” on page 68 for more details.

Bit 7 6 5 4 3 2 1 0

COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 TCCR0A

Read/Write R/W R/W R/W R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 34. Compare Output Mode, non-PWM Mode

COM0A1 COM0A0 Description

0 0 Normal port operation, OC0A disconnected.

0 1 Toggle OC0A on Compare Match

1 0 Clear OC0A on Compare Match

1 1 Set OC0A on Compare Match

Table 35. Compare Output Mode, Fast PWM Mode

(1)

COM0A1 COM0A0 Description

0 0 Normal port operation, OC0A disconnected.

0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected.

WGM02 = 1: Toggle OC0A on Compare Match.

1 0 Clear OC0A on Compare Match, set OC0A at TOP

1 1 Set OC0A on Compare Match, clear OC0A at TOP