Datasheet

60
ATtiny2313/V
2543H–AVR–02/05
activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin
will cause an interrupt request even if INT1 is configured as an output. The correspond-
ing interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU Control Register – MCUCR – define whether the external interrupt is
activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin
will cause an interrupt request even if INT0 is configured as an output. The correspond-
ing interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.
• Bit 5 – PCIE: Pin Change Interrupt Enable
When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 1 is enabled. Any change on any enabled PCINT7..0 pin will cause
an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCI Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK
Register.