Datasheet

ATtiny2313/V

2543H–AVR–02/05

External Interrupts The External Interrupts are triggered by the INT0 pin, INT1 pin or any of the PCINT7..0

pins. Observe that, if enabled, the interrupts will trigger even if the INT0, INT1or

PCINT7..0 pins are configured as outputs. This feature provides a way of generating a

software interrupt. The pin change interrupt PCI1 will trigger if any enabled PCINT7..8

pin toggles. Pin change interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles.

The PCMSK1 and PCMSK0 Registers control which pins contribute to the pin change

interrupts. Pin change interrupts on PCINT7..0 are detected asynchronously. This

implies that these interrupts can be used for waking the part also from sleep modes

other than Idle mode.

The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level.

This is set up as indicated in the specification for the External Interrupt Control Register

A – EICRA. When the INT0 or INT1 interrupt is enabled and is configured as level trig-

gered, the interrupt will trigger as long as the pin is held low. Note that recognition of

falling or rising edge interrupts on INT0 and INT1 requires the presence of an I/O clock,

described in “Clock Systems and their Distribution” on page 21. Low level interrupt on

INT0 and INT1 is detected asynchronously. This implies that this interrupt can be used

for waking the part from sleep modes other than Idle mode. The I/O clock is halted in all

sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down, the

required level must be held long enough for the MCU to complete the wake-up to trigger

the level interrupt. If the level disappears before the end of the Start-up Time, the MCU

will still wake up, but no interrupt will be generated. The start-up time is defined by the

SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 21.

Pin Change Interrupt

Timing

An example of timing of a pin change interrupt is shown in Figure 26.

Figure 26.

clk

PCINT(n)

pin_lat

pin_sync

pcint_in_(n)

pcint_syn

pcint_setflag

PCIF

PCINT(0)

pin_sync

pcint_syn

pin_lat

D Q

pcint_setflag

PCIF

clk

PCINT(0) in PCMSK(x)

pcint_in_(0)