Datasheet

109
ATtiny2313/V
2543H–AVR–02/05
Output Compare Register 1 B
- OCR1BH and OCR1BL
The Output Compare Registers contain a 16-bit value that is continuously compared
with the counter value (TCNT1). A match can be used to generate an Output Compare
interrupt, or to generate a waveform output on the OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low
bytes are written simultaneously when the CPU writes to these registers, the access is
performed using an 8-bit temporary high byte register (TEMP). This temporary register
is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 84.
Input Capture Register 1 –
ICR1H and ICR1L
The Input Capture is updated with the counter (TCNT1) value each time an event occurs
on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1).
The Input Capture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes
are read simultaneously when the CPU accesses these registers, the access is per-
formed using an 8-bit temporary high byte register (TEMP). This temporary register is
shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 84.
Timer/Counter Interrupt Mask
Register – TIMSK
• Bit 7 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 43.) is executed when the TOV1 flag, located
in TIFR, is set.
• Bit 6 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 43.) is executed when the
OCF1A flag, located in TIFR, is set.
• Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The
corresponding Interrupt Vector (See “Interrupts” on page 43.) is executed when the
OCF1B flag, located in TIFR, is set.
• Bit 3 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
Bit 76543210
OCR1B[15:8] OCR1BH
OCR1B[7:0] OCR1BL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
ICR1[15:8] ICR1H
ICR1[7:0] ICR1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 7 6 5 4 3 2 1 0
TOIE1 OCIE1A OCIE1B
–ICIE1OCIE0B TOIE0 OCIE0A TIMSK
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0