Features • Utilizes the AVR® RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz Data and Non-volatile Program and Data Memories – 2K Bytes of In-System Self Programmable Flash Endurance 10,000 Write/Erase Cycles – 128 Bytes In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – 128 By
Pin Configurations Figure 1.
ATtiny2313/V Block Diagram Figure 2. Block Diagram XTAL1 XTAL2 PA0 - PA2 PORTA DRIVERS VCC DATA DIR. REG.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATtiny2313/V Pin Descriptions VCC Digital supply voltage. GND Ground. Port A (PA2..PA0) Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated.
AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 3.
ATtiny2313/V the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The AVR Status Register – SREG – is defined as: Bit 7 6 5 4 3 2 1 0 I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
ATtiny2313/V Figure 4. AVR CPU General Purpose Working Registers 7 0 Addr.
Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located.
ATtiny2313/V Figure 7. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space.
neously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence..
ATtiny2313/V AVR ATtiny2313 Memories This section describes the different memories in the ATtiny2313. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATtiny2313 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. In-System Reprogrammable Flash Program Memory The ATtiny2313 contains 2K bytes On-chip In-System Reprogrammable Flash memory for program storage.
SRAM Data Memory Figure 9 shows how the ATtiny2313 SRAM Memory is organized. The lower 224 data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O memory, and the next 128 locations address the internal data SRAM.
ATtiny2313/V Figure 10. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Address valid Compute Address Write Data WR Read Data RD Memory Access Instruction Next Instruction EEPROM Data Memory The ATtiny2313 contains 128 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
• Bits 6..0 – EEAR6..0: EEPROM Address The EEPROM Address Register – EEAR specify the EEPROM address in the 128 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 127. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. The EEPROM Data Register – EEDR Bit 7 6 5 4 3 2 1 0 MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EEDR • Bits 7..0 – EEDR7..
ATtiny2313/V • Bit 2 – EEMPE: EEPROM Master Program Enable The EEMPE bit determines whether writing EEPE to one will have effect or not. When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles.
The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in “Oscillator Calibration Register – OSCCAL” on page 25. The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATtiny2313/V The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
I/O Memory The I/O space definition of the ATtiny2313 is shown in “Register Summary” on page 211. All ATtiny2313 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
ATtiny2313/V System Clock and Clock Options Clock Systems and their Distribution Figure 11 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 29. The clock systems are detailed below. Figure 11.
Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 2. Device Clocking Select(1) Device Clocking Option CKSEL3..
ATtiny2313/V Figure 12. Crystal Oscillator Connections C2 C1 XTAL2 XTAL1 GND The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 4. Table 4. Crystal Oscillator Operating Modes CKSEL3..1 Frequency Range(1) (MHz) Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) 100(2) 0.4 - 0.9 – 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 12 - 22 Notes: 1.
Table 5. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 (1) Additional Delay from Reset (VCC = 5.0V) Recommended Usage 0 00 258 CK 14CK + 4.1 ms Ceramic resonator, fast rising power 0 01 258 CK(1) 14CK + 65 ms Ceramic resonator, slowly rising power 0 10 1K CK(2) 14CK Ceramic resonator, BOD enabled 0 11 1K CK(2) 14CK + 4.
ATtiny2313/V When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 7. Table 7. Start-up times for the internal calibrated RC Oscillator clock selection SUT1..0 Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) 00 6 CK 14CK 01 6 CK 14CK + 4.1 ms Fast rising power 10(1) 6 CK 14CK + 65 ms Slowly rising power 11 Note: Oscillator Calibration Register – OSCCAL Recommended Usage BOD enabled Reserved 1.
External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 13. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. Figure 13. External Clock Drive Configuration NC XTAL2 EXTERNAL CLOCK SIGNAL XTAL1 GND When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 10. Table 9. Crystal Oscillator Clock Frequency CKSEL3..0 Frequency Range 0000 - 0001 0 - 16 MHz Table 10.
ATtiny2313/V 128 kHz Internal Oscillator The 128 kHz Internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency is nominal at 3 V and 25°C. This clock may be selected as the system clock by programming the CKSEL Fuses to “0110 - 0111”. When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 11. Table 11. Start-up Times for the 128 kHz Internal Oscillator SUT1..
frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 12.
ATtiny2313/V Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the three sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed.
Power-down Mode When the SM1..0 bits are written to 01 or 11, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the USI start condition detection, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU.
ATtiny2313/V Brown-out Detector If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Brown-out Detection” on page 34 for details on how to configure the Brown-out Detector.
System Control and Reset Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be an RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 14 shows the reset logic.
ATtiny2313/V Table 15. Reset Characteristics Symbol Condition Min(1) Typ(1) Max(1) Units Power-on Reset Threshold Voltage (rising) TA = -40 - 85°C 1.2 V Power-on Reset Threshold Voltage (falling)(2) TA = -40 - 85°C 1.1 V VRST RESET Pin Threshold Voltage VCC = 1.8 - 5.5V tRST Minimum pulse width on RESET Pin VCC = 1.8 - 5.5V VPOT Notes: Power-on Reset Parameter 0.2 VCC 0.9 VCC V 2.5 µs 1. Values are guidelines only. Actual values are TBD. 2.
Figure 16. MCU Start-up, RESET Extended Externally VPOT VCC VRST RESET tTOUT TIME-OUT INTERNAL RESET External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 15) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
ATtiny2313/V Table 16. BODLEVEL Fuse Coding(1) BODLEVEL 2..0 Fuses Min VBOT Typ VBOT Max VBOT Units 011 010 Reserved 001 000 Note: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-Out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed.
Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 43 for details on operation of the Watchdog Timer. Figure 19. Watchdog Reset During Operation CC CK MCU Status Register – MCUSR The MCU Status Register provides information on which reset source caused an MCU reset.
ATtiny2313/V Internal Voltage Reference ATtiny2313 features an internal bandgap reference. This reference is used for Brownout Detection, and it can be used as an input to the Analog Comparator. Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 18. To save power, the reference is not always turned on. The reference is on during the following situations: 1.
Watchdog Timer ATtiny2313 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 128kHz OSCILLATOR WATCHDOG RESET WDE OSC/2K OSC/4K OSC/8K OSC/16K OSC/32K OSC/64K OSC/128K OSC/256K OSC/512K OSC/1024K Figure 20.
ATtiny2313/V The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.
Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use. The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer.
ATtiny2313/V Watchdog Timer Control Register - WDTCSR Bit 7 6 5 4 3 2 1 0 WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 X 0 0 0 WDTCSR • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector.
Table 20. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V 0 0 0 0 2K (2048) cycles 16 ms 0 0 0 1 4K (4096) cycles 32 ms 0 0 1 0 8K (8192) cycles 64 ms 0 0 1 1 16K (16384) cycles 0.125 s 0 1 0 0 32K (32768) cycles 0.25 s 0 1 0 1 64K (65536) cycles 0.5 s 0 1 1 0 128K (131072) cycles 1.0 s 0 1 1 1 256K (262144) cycles 2.0 s 1 0 0 0 512K (524288) cycles 4.
ATtiny2313/V Interrupts Interrupt Vectors in ATtiny2313 This section describes the specifics of the interrupt handling as performed in ATtiny2313. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 11. Table 21. Reset and Interrupt Vectors Vector No.
The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny2313 is: Address Labels Code Comments 0x0000 rjmp RESET ; Reset Handler 0x0001 rjmp INT0 ; External Interrupt0 Handler 0x0002 rjmp INT1 ; External Interrupt1 Handler 0x0003 rjmp TIM1_CAPT ; Timer1 Capture Handler 0x0004 rjmp TIM1_COMPA ; Timer1 CompareA Handler 0x0005 rjmp TIM1_OVF ; Timer1 Overflow Handler 0x0006 rjmp TIM0_OVF ; Timer0 Overflow Handler 0x0007 rjmp USART0_RXC ; U
ATtiny2313/V I/O-Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 22 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 22.
ATtiny2313/V Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur.
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge.
ATtiny2313/V The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ...
Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 25 shows how the port pin control signals from the simplified Figure 22 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 25.
ATtiny2313/V Table 23. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
MCU Control Register – MCUCR Bit 7 6 5 4 3 2 1 0 PUD SM1 SE SM0 ISC11 ISC10 ISC01 ISC00 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 7 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 46 for more details about this feature.
ATtiny2313/V DI: Three-wire mode Universal Serial Interface Data input. Three-wire mode does not override normal port functions, so pin must be configured as an input. SDA: Two-wire mode Serial Interface Data. PCINT5: Pin Change Interrupt Source 5. The PB5 pin can serve as an external interrupt source. • OC1B/PCINT4 – Port B, Bit 4 OC1B: Output Compare Match B output: The PB4 pin can serve as an external output for the Timer/Counter1 Output Compare B.
Table 26. Overriding Signals for Alternate Functions in PB7..
ATtiny2313/V Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 28. Table 28. Port D Pins Alternate Functions Port Pin Alternate Function PD6 ICP PD5 OC0B/T1 PD4 T0 PD3 INT1 PD2 INT0/XCK/CKOUT PD1 TXD PD0 RXD The alternate pin configuration is as follows: • ICP – Port D, Bit 6 ICP: Timer/Counter1 Input Capture Pin.
Table 29 and Table 30 relates the alternate functions of Port D to the overriding signals shown in Figure 25 on page 50. Table 29. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PD6/ICP PD5/OC1B/T1 PD4/T0 PUOE 0 0 0 PUOV 0 0 0 DDOE 0 0 0 DDOV 0 0 0 PVOE 0 OC1B_PVOE 0 PVOV 0 OC1B_PVOV 0 PTOE 0 0 0 DIEOE ICP ENABLE T1 ENABLE T0 ENABLE DIEOV 1 1 1 DI ICP INPUT T1 INPUT T0 INPUT AIO – – AIN1 Table 30.
ATtiny2313/V Register Description for I/O-Ports Port A Data Register – PORTA Bit Port A Data Direction Register – DDRA Port A Input Pins Address – PINA 7 6 5 4 3 2 1 0 – – – – – PORTA2 PORTA1 PORTA0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 – – – – – DDA2 DDA1 DDA0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 – – – – – PINA2 PINA1 PINA0 Read/
External Interrupts The External Interrupts are triggered by the INT0 pin, INT1 pin or any of the PCINT7..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0, INT1or PCINT7..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI1 will trigger if any enabled PCINT7..8 pin toggles. Pin change interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles.
ATtiny2313/V MCU Control Register – MCUCR The External Interrupt Control Register A contains control bits for interrupt sense control. Bit 7 6 5 4 3 2 1 0 PUD SM1 SE SMD ISC11 ISC10 ISC01 ISC00 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.
activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
ATtiny2313/V External Interrupt Flag Register – EIFR Bit 7 6 5 4 3 2 1 INTF1 INTF0 PCIF – – – – 0 – Read/Write R/W R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 EIFR • Bit 7 – INTF1: External Interrupt Flag 1 When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector.
8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event management) and wave generation.
ATtiny2313/V Compare pins (OC0A and OC0B). See “Output Compare Unit” on page 64. for details. The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt request. Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare Unit, in this case Compare Unit A or Compare Unit B.
Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
ATtiny2313/V The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
Figure 30. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCn Waveform Generator D Q 1 OCnx DATA BUS D 0 OCn Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
ATtiny2313/V Normal Mode The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero.
mum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCnx = ------------------------------------------------2 ⋅ N ⋅ ( 1 + OCRnx ) The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00.
ATtiny2313/V inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows the AC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 26 on page 54). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output.
Figure 33. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCn (COMnx1:0 = 2) OCn (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
ATtiny2313/V Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. • Timer/Counter Timing Diagrams The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures.
Figure 37 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where OCR0A is TOP. Figure 37.
ATtiny2313/V 8-bit Timer/Counter Register Description Timer/Counter Control Register A – TCCR0A Bit 7 6 5 4 3 2 1 0 COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior.
Table 36 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 36. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. 1 1 Set OC0A on Compare Match when up-counting.
ATtiny2313/V Table 39 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 39. Compare Output Mode, Phase Correct PWM Mode(1) COM0B1 COM0B0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting. 1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting. Note: Description 1.
Timer/Counter Control Register B – TCCR0B Bit 7 6 5 4 3 2 1 0 FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode.
ATtiny2313/V Table 41. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge.
Timer/Counter Interrupt Mask Register – TIMSK Bit 7 6 5 4 3 2 1 0 TOIE1 OCIE1A OCIE1B – ICIE1 OCIE0B TOIE0 OCIE0A Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK • Bit 4 – Res: Reserved Bit This bit is reserved bit in the ATtiny2313 and will always read as zero.
ATtiny2313/V The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Output Compare Register0 A. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O).
ATtiny2313/V the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 39.
16-bit Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e.
ATtiny2313/V Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the section “Accessing 16-bit Registers” on page 84. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req.
The following control bits have changed name, but have same functionality and register location: • PWM10 is changed to WGM10. • PWM11 is changed to WGM11. • CTC1 is changed to WGM12. The following bits are added to the 16-bit Timer/Counter Control Registers: • FOC1A and FOC1B are added to TCCR1A. • WGM13 is added to TCCR1B. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases.
ATtiny2313/V Assembly Code Examples(1) ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... C Code Examples(1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1; ... Note: 1. The example code assumes that the part specific header file is included.
The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATtiny2313/V The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 80. Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
ATtiny2313/V how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 94. The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.
The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Generation mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 84.
ATtiny2313/V Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF1x flag is automatically cleared when the interrupt is executed.
(Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Register since the compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be written first.
ATtiny2313/V Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 44 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the OC1x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 43 on page 104. For fast PWM mode refer to Table 44 on page 104, and for phase correct and phase and frequency correct PWM refer to Table 45 on page 105.
ATtiny2313/V Figure 45. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is set on the compare match between TCNT1 and OCR1x, and cleared at TOP.
ATtiny2313/V When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x Registers are written. The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value.
Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM.
ATtiny2313/V The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag is set accordingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at TOP). The interrupt flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value.
Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM.
ATtiny2313/V The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag set when TCNT1 has reached TOP. The interrupt flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value.
Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 49 shows a timing diagram for the setting of OCF1x. Figure 49.
ATtiny2313/V Figure 51. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value Figure 52 shows the same timing data, but with the prescaler enabled. Figure 52.
16-bit Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1A • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respectively) behavior.
ATtiny2313/V Table 45 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 45. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13=0: Normal port operation, OC1A/OC1B disconnected. WGM13=1: Toggle OC1A on Compare Match, OC1B reserved. 1 0 Clear OC1A/OC1B on Compare Match when upcounting.
Table 46.
ATtiny2313/V Timer/Counter1 Control Register B – TCCR1B Bit 7 6 5 4 3 2 1 0 ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1B • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP1) is filtered.
Timer/Counter1 Control Register C – TCCR1C Bit 7 6 5 4 3 2 1 0 FOC1A FOC1B – – – – – – Read/Write W W R R R R R R Initial Value 0 0 0 0 0 0 0 0 TCCR1C • Bit 7 – FOC1A: Force Output Compare for Channel A • Bit 6 – FOC1B: Force Output Compare for Channel B The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode.
ATtiny2313/V Output Compare Register 1 B - OCR1BH and OCR1BL Bit 7 6 5 4 3 2 1 0 OCR1B[15:8] OCR1BH OCR1B[7:0] OCR1BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC1x pin. The Output Compare Registers are 16-bit in size.
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 43.) is executed when the ICF1 flag, located in TIFR, is set.
ATtiny2313/V USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device.
The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units. The Clock Generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only used by synchronous transfer mode.
ATtiny2313/V Figure 54. Clock Generation Logic, Block Diagram UBRR U2X fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 0 1 0 OSC DDR_XCK xcki XCK Pin Sync Register Edge Detector xcko DDR_XCK 1 0 UMSEL 1 UCPOL txclk 1 0 rxclk Signal description: Internal Clock Generation – The Baud Rate Generator txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.
Table 48.
ATtiny2313/V Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. Figure 55. Synchronous Mode XCK Timing.
Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame.
ATtiny2313/V The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers.
Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions. If synchronous operation is used, the clock on the XCK pin will be overridden and used as transmission clock.
ATtiny2313/V Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written to UDR. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
Transmitter Flags and Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDRE) and Transmit Complete (TXC). Both flags can be used for generating interrupts. The Data Register Empty (UDRE) flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register.
ATtiny2313/V Data Reception – The USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the Receiver’s serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCK pin will be used as transfer clock.
Receiving Frames with 9 Data Bits If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR and UPE Status Flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR and UPE bits, which all are stored in the FIFO, will change.
ATtiny2313/V Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. The receive function example reads all the I/O Registers into the Register File before any computation is done.
Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of Parity Check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits.
ATtiny2313/V Asynchronous Clock Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 57 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the Double Speed mode (U2X = 1) of operation.
Figure 59 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. Figure 59. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample (U2X = 1) 1 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FE) flag will be set.
ATtiny2313/V Table 49. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11/-5.19 ± 2.0 8 95.36 104.58 +4.58/-4.54 ± 2.0 9 95.81 104.14 +4.14/-4.19 ± 1.5 10 96.17 103.78 +3.78/-3.83 ± 1.5 Table 50.
Multi-processor Communication Mode Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a filtering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. This effectively reduces the number of incoming frames that has to be handled by the CPU, in a system with multiple MCUs that communicate via the same serial bus.
ATtiny2313/V USART Register Description USART I/O Data Register – UDR Bit 7 6 5 4 3 2 1 0 RXB[7:0] UDR (Read) TXB[7:0] UDR (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDR. The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDR Register location.
• Bit 5 – UDRE: USART Data Register Empty The UDRE flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDRE is one, the buffer is empty, and therefore ready to be written. The UDRE flag can generate a Data Register Empty interrupt (see description of the UDRIE bit). UDRE is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FE: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e.
ATtiny2313/V USART Control and Status Register B – UCSRB Bit 7 6 5 4 3 2 1 0 RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 UCSRB • Bit 7 – RXCIE: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC flag.
USART Control and Status Register C – UCSRC Bit 7 6 5 4 3 2 1 0 – UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 1 1 0 UCSRC • Bit 6 – UMSEL: USART Mode Select This bit selects between asynchronous and synchronous mode of operation. Table 51.
ATtiny2313/V Table 54. UCSZ Bits Settings UCSZ2 UCSZ1 UCSZ0 Character Size 0 0 0 5-bit 0 0 1 6-bit 0 1 0 7-bit 0 1 1 8-bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9-bit • Bit 0 – UCPOL: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK). Table 55.
Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 56. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table.
ATtiny2313/V Table 57. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz Baud Rate (bps) UBRR 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.
Table 58. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000 MHz fosc = 14.7456 MHz Baud Rate (bps) UBRR 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.
ATtiny2313/V Table 59. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000 MHz Baud Rate (bps) U2X = 0 UBRR U2X = 1 Error UBRR Error 2400 416 -0.1% 832 0.0% 4800 207 0.2% 416 -0.1% 9600 103 0.2% 207 0.2% 14.4k 68 0.6% 138 -0.1% 19.2k 51 0.2% 103 0.2% 28.8k 34 -0.8% 68 0.6% 38.4k 25 0.2% 51 0.2% 57.6k 16 2.1% 34 -0.8% 76.8k 12 0.2% 25 0.2% 115.2k 8 -3.5% 16 2.1% 230.4k 3 8.5% 8 -3.5% 250k 3 0.0% 7 0.
Universal Serial Interface – USI The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load.
ATtiny2313/V The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It can also generate wait states by holding the clock pin low after a start condition is detected, or after the counter overflows. Functional Descriptions Three-wire Mode The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the slave select (SS) pin functionality.
The Three-wire mode timing is shown in Figure 62. At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes. In External Clock mode 0 (USICS0 = 0), DI is sampled at positive edges, and DO is changed (data register is shifted by one) at negative edges. External Clock mode 1 (USICS0 = 1) uses the opposite edges versus mode 0, i.e.
ATtiny2313/V The following code demonstrates how to use the USI module as a SPI Master with maximum speed (fsck = fck/2): SPITransfer_Fast: out USIDR,r16 ldi r16,(1<
ferred to the master device, and when the transfer is completed the data received from the Master is stored back into the r16 Register. Note that the first two instructions is for initialization only and needs only to be executed once.These instructions sets Three-wire mode and positive edge Shift Register clock. The loop is repeated until the USI Counter Overflow Flag is set. Two-wire Mode The USI Two-wire mode does not incorporate slew rate limiting on outputs and input noise filtering.
ATtiny2313/V Figure 64. Two-wire Mode, Typical Timing Diagram SDA SCL S A B 1-7 8 9 1-8 9 1-8 9 ADDRESS R/W ACK DATA ACK DATA ACK C D E P F Referring to the timing diagram (Figure 64.), a bus transfer involves the following steps: 1. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift Register, or by setting the corresponding bit in the PORT Register to zero.
Start Condition Detector The start condition detector is shown in Figure 65. The SDA line is delayed (in the range of 50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is working asynchronously and can therefore wake up the processor from the Power-down sleep mode. However, the protocol used might have restrictions on the SCL hold time.
ATtiny2313/V Note that the corresponding Data Direction Register to the pin must be set to one for enabling data output from the Shift Register. USI Status Register – USISR Bit 7 6 5 4 3 2 1 0 USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 USISR The Status Register contains interrupt flags, line status flags and the counter value.
USI Control Register – USICR Bit 7 6 5 4 3 2 1 0 USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC Read/Write R/W R/W R/W R/W R/W R/W W W Initial Value 0 0 0 0 0 0 0 0 USICR The Control Register includes interrupt enable control, wire mode setting, Clock Select setting, and clock strobe. • Bit 7 – USISIE: Start Condition Interrupt Enable Setting this bit to one enables the Start Condition detector interrupt.
ATtiny2313/V Table 60. Relations between USIWM1..0 and the USI Operation USIWM1 USIWM0 0 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal. 0 1 Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORT Register in this mode. However, the corresponding DDR bit still controls the data direction. When the port pin is set as input the pins pull-up is controlled by the PORT bit.
• Bit 3..2 – USICS1..0: Clock Source Select These bits set the clock source for the Shift Register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of the data input (DI/SDA) when using external clock source (USCK/SCL). When software strobe or Timer0 overflow clock option is selected, the output latch is transparent and therefore the output is changed immediately. Clearing the USICS1..0 bits enables software strobe option.
ATtiny2313/V Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled. • Bit 2 – ACIC: Analog Comparator Input Capture Enable When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the Analog Comparator.
ATtiny2313/V debugWIRE On-chip Debug System Features • • • • • • • • • • Overview The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the program flow, execute AVR instructions in the CPU and to program the different non-volatile memories. Physical Interface When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE system within the target device is activated.
Software Break Points • Capacitors inserted on the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a Break Point in AVR Studio ® will insert a BREAK instruction in the Program memory. The instruction replaced by the BREAK instruction will be stored.
ATtiny2313/V Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The Program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
Addressing the Flash During SelfProgramming The Z-pointer is used to address the SPM commands. Bit 15 14 13 12 11 10 9 8 ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 7 6 5 4 3 2 1 0 Since the Flash is organized in pages (see Table 69 on page 160), the Program Counter can be treated as having two different sections.
ATtiny2313/V Store Program Memory Control and Status Register – SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to control the Program memory operations. Bit 7 6 5 4 3 2 1 0 – – – CTPB RFLB PGWRT PGERS SELFPRGEN Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPMCSR • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313 and always read as zero.
EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software.
ATtiny2313/V Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly.
Memory Programming Program And Data Memory Lock Bits The ATtiny2313 provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 65. The Lock bits can only be erased to “1” with the Chip Erase command. Table 64.
ATtiny2313/V Fuse Bits The ATtiny2313 has three Fuse bytes. Table 67 and Table 68 describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 66.
Table 68. Fuse Low Byte Fuse Low Byte Bit No Description Default Value CKDIV8 7 Divide clock by 8 0 (programmed) CKOUT 6 Output Clock on CKOUT pin 1 (unprogrammed) SUT1 5 Select start-up time 1 (unprogrammed)(1) SUT0 4 Select start-up time 0 (programmed)(1) CKSEL3 3 Select Clock source 0 (programmed)(2) CKSEL2 2 Select Clock source 1 (unprogrammed)(2) CKSEL1 1 Select Clock source 0 (programmed)(2) CKSEL0 0 Select Clock source 0 (programmed)(2) Note: 1.
ATtiny2313/V Table 70. No. of Words in a Page and No. of Pages in the EEPROM EEPROM Size Page Size PCWORD No. of Pages PCPAGE EEAMSB 128 bytes 4 bytes EEA[1:0] 32 EEA[6:2] 6 Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATtiny2313. Pulses are assumed to be at least 250 ns unless otherwise noted.
Table 71. Pin Name Mapping (Continued) Signal Name in Programming Mode Pin Name I/O XA0 PD5 I XTAL Action Bit 0 XA1/BS2 PD6 I XTAL Action Bit 1. Byte Select 2 (“0” selects low byte, “1” selects 2’nd high byte). DATA I/O PB7-0 I/O Function Bi-directional Data bus (Output when OE is low). Table 72. Pin Values Used to Enter Programming Mode Pin Symbol Value XA1 Prog_enable[3] 0 XA0 Prog_enable[2] 0 BS1 Prog_enable[1] 0 WR Prog_enable[0] 0 Table 73.
ATtiny2313/V Serial Programming Pin Mapping Table 75. Pin Mapping Serial Programming Symbol Pins I/O Description MOSI PB5 I Serial Data in MISO PB6 O Serial Data out SCK PB7 I Serial Clock Parallel Programming Enter Programming Mode The following algorithm puts the device in Parallel programming mode: 1. Set Prog_enable pins listed in Table 72 on page 162 to “0000”, RESET pin VCC to 0V. 2. Apply 4.5 - 5.5V between VCC and GND. 3. Ensure that VCC reaches at least 1.8V within the next 20 µs.
are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed. Note: 1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed. Load Command “Chip Erase” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “1000 0000”. This is the command for Chip Erase. 4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 6.
ATtiny2313/V Programming the Flash The Flash is organized in pages, see Table 69 on page 160. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4.
1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 70. Addressing the Flash Which is Organized in Pages(1) PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: 1.
ATtiny2313/V Programming the EEPROM The EEPROM is organized in pages, see Table 70 on page 161. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash” on page 165 for details on Command, Address and Data loading): 1. A: Load Command “0001 0001”. 2. G: Load Address High Byte (0x00 - 0xFF). 3.
Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash” on page 165 for details on Command and Address loading): 1. A: Load Command “0000 0011”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”.
ATtiny2313/V Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 165 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed (LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any External Programming mode. 3. Give WR a negative pulse and wait for RDY/BSY to go high.
Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to “Programming the Flash” on page 165 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte, 0x00. 3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA. 4. Set OE to “1”. Parallel Programming Characteristics Figure 75.
ATtiny2313/V Figure 77. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE tOHDZ DATA ADDR0 (Low Byte) ADDR1 (Low Byte) DATA (High Byte) DATA (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 75 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 76.
Table 76. Parallel Programming Characteristics, VCC = 5V ± 10% (Continued) Symbol Parameter tBVDV BS1 Valid to DATA valid tOLDV tOHDZ Notes: Serial Downloading Min Max Units 250 ns OE Low to DATA Valid 250 ns OE High to DATA Tri-stated 250 ns 0 Typ 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. tWLRH_CE is valid for the Chip Erase command.
ATtiny2313/V Serial Programming Algorithm When writing serial data to the ATtiny2313, data is clocked on the rising edge of SCK. When reading data from the ATtiny2313, data is clocked on the falling edge of SCK. See Figure 79, Figure 80 and Table 79 for timing details. To program and verify the ATtiny2313 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 78 on page 174): 1.
Table 77. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 4.0 ms tWD_ERASE 4.0 ms tWD_FUSE 4.5 ms Figure 79. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Table 78.
ATtiny2313/V Table 78. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Read Lock bits 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits. “0” = programmed, “1” = unprogrammed. See Table 64 on page 158 for details. Write Lock bits 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits. Set bits = “0” to program Lock bits. See Table 64 on page 158 for details.
Serial Programming Characteristics Figure 80. Serial Programming Timing MOSI tSHOX tOVSH SCK tSLSH tSHSL MISO tSLIV Table 79. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 2.7V - 5.5V (Unless Otherwise Noted) Symbol Parameter 1/tCLCL Oscillator Frequency (ATtiny2313L) Oscillator Period (ATtiny2313L) tCLCL Typ 0 Max Units 8 MHz 125 ns Oscillator Frequency (ATtiny2313, VCC = 4.5V 5.5V) 0 tCLCL Oscillator Period (ATtiny2313, VCC = 4.5V 5.
ATtiny2313/V Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)(1) (Continued) Symbol Parameter Condition Power Supply Current ICC Power-down mode Notes: Min. Typ. Max. Units Active 1MHz, VCC = 2V 0.35 mA Active 4MHz, VCC = 3V 2 mA Active 8MHz, VCC = 5V 6 mA Idle 1MHz, VCC = 2V 0.08 0.2 mA Idle 4MHz, VCC = 3V 0.41 1 mA Idle 8MHz, VCC = 5V 1.6 3 mA WDT enabled, VCC = 3V <3 6 µA WDT disabled, VCC = 3V < 0.5 2 µA 1.
ATtiny2313/V Table 80. External Clock Drive (Estimated Values) VCC = 1.8 - 5.5V Symbol Parameter tCLCH Rise Time 2.0 tCHCL Fall Time ∆tCLCL Change in period from one clock cycle to the next Min. Max. VCC = 2.7 - 5.5V Min. Max. VCC = 4.5 - 5.5V Min. Max. Units 1.6 0.5 µs 2.0 1.6 0.
Maximum Speed vs. VCC Maximum frequency is dependent on VCC. As shown in Figure 82 and Figure 83, the Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V. Figure 82. Maximum Frequency vs. VCC, ATtiny2313V 10 MHz Safe Operating Area 4 MHz 1.8V 2.7V 5.5V Figure 83. Maximum Frequency vs. VCC, ATtiny2313 20 MHz 10 MHz Safe Operating Area 2.7V 180 4.5V 5.
ATtiny2313/V ATtiny2313 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
Figure 85. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 14 5.5 V 12 5.0 V ICC (mA) 10 4.5 V 8 6 4.0 V 3.3 V 2.7 V 4 2 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 86. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 9 85 ˚C 25 ˚C -40 ˚C 8 7 ICC (mA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny2313/V Figure 87. Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) ACTIVE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 4 MHz 6 -40 °C 85 °C 25 °C 5 Icc (mA) 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 88. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 1 MHz 1.8 85 °C 25 °C -40 °C 1.6 1.4 Icc (mA) 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 89. Active Supply Current vs. VCC (Internal RC Oscillator, 0.5 MHz) ACTIVE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 0.5 MHz 1.2 1 85 °C 25 °C -40 °C Icc (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 90. Active Supply Current vs. VCC (Internal RC Oscillator, 128 KHz) ACTIVE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 128 KHz 0.14 -40 °C 25 °C 85 °C 0.12 Icc (mA) 0.1 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny2313/V Idle Supply Current Figure 91. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz 0.25 5.5 V 0.2 5.0 V I cc (m A) 4.5 V 0.15 4.0 V 3.3 V 0.1 2.7 V 1.8 V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 92. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 5 4.5 5.5 V 4 5.0 V 3.5 4.5 V I cc (mA) 3 2.5 2 1.5 4.0 V 3.3 V 2.7 V 1 0.5 1.
Figure 93. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 8 MHz 3 85 °C 25 °C -40 °C 2.5 Icc (mA) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 94. Idle Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) IDLE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 4 MHz 1.6 85 °C 25 °C -40 °C 1.4 1.2 Icc (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny2313/V Figure 95. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 1 MHz 0.5 85 °C 25 °C -40 °C 0.4 Icc (mA) 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 96. Idle Supply Current vs. VCC (Internal RC Oscillator, 0.5 MHz) IDLE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 0.5 MHz 0.3 85 °C 25 °C -40 °C 0.25 Icc (mA) 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 97. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 KHz) IDLE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 128 KHz 0.035 -40 °C 25 °C 85 °C 0.03 I cc (m A) 0.025 0.02 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Power-down Supply Current Figure 98. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER DISABLED 1.5 85 °C 1.25 I cc (uA) 1 -40 °C 0.75 25 °C 0.5 0.25 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny2313/V Figure 99. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER ENABLED 20 85 °C 18 25 °C -40 °C 16 14 Icc (uA) 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Standby Supply Current Figure 100. Standby Supply Current vs. VCC STANDBY SUPPLY CURRENT vs. Vcc 0.08 2MHz Res 2MHz Xtal 0.07 0.06 455KHz Res 1MHz Res I cc (m A) 0.05 0.04 0.03 0.02 0.01 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Pin Pull-up Figure 101. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 160 140 85 °C 25 °C 120 -40 °C I OP (uA ) 100 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) Figure 102. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 80 25 °C 85 °C 70 -40 °C 60 IOP (uA) 50 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATtiny2313/V Figure 103. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 5V 120 25 °C -40 °C 100 85 °C IRESET (uA) 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET(V) Figure 104. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 2.7V 60 25 °C -40 °C 50 85 °C IRESET (uA) 40 30 20 10 0 0 0.5 1 1.5 2 2.
Pin Driver Strength Figure 105. I/O Pin Source Current vs. Output Voltage (VCC = 5V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 90 80 85 °C 70 60 -40 °C IOH (mA) 25 °C 50 40 30 20 10 0 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 VOH (V) Figure 106. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 35 30 25 -40 °C 25 °C IOH (mA) 85 °C 20 15 10 5 0 0.5 1 1.5 2 2.
ATtiny2313/V Figure 107. I/O Pin Source Current vs. Output Voltage (VCC = 1.8V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 1.8V 9 -40 °C 25 °C 8 85 °C 7 IOH (mA) 6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH (V) Figure 108. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 100 -40 °C 90 80 25 °C 70 85 °C IOL (mA) 60 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 109. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 40 35 -40 °C 30 25 °C IOL (mA) 25 85 °C 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) Figure 110. I/O Pin Sink Current vs. Output Voltage (VCC = 1.8V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 1.8V 14 12 -40 °C 10 25 °C IOL (mA) 85 °C 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATtiny2313/V Figure 111. Reset I/O Pin Source Current vs. Output Voltage (VCC = 5V) RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 16 -40 °C 14 12 Current (mA) 25 °C 10 8 85 °C 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOH (V) Figure 112. Reset I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 4.5 4 -40 °C 3.5 25 °C Current (m A) 3 2.5 85 °C 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.
Figure 113. Reset I/O Pin Source Current vs. Output Voltage (VCC = 1.8V) RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 1.8V 1.4 -40 °C 1.2 25 °C Current (mA) 1 0.8 85 °C 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH (V) Figure 114. Reset I/O Pin Sink Current vs. Output Voltage (VCC = 5V) RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 16 -40 °C Current (mA) 14 12 25 °C 10 85 °C 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATtiny2313/V Figure 115. Reset I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 4.5 -40 °C Current (mA) 4 3.5 25 °C 3 85 °C 2.5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOL (V) Figure 116. Reset I/O Pin Sink Current vs. Output Voltage (VCC = 1.8V) RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 1.8V 1.4 -40 °C 1.2 25 °C 85 °C Current (mA) 1 0.8 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Pin Thresholds and Hysteresis Figure 117. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc VIH, IO PIN READ AS '1' 3 85 °C -40 °C 25 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 118. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc VIL, IO PIN READ AS '0' 3 85 °C 25 °C -40 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.
ATtiny2313/V Figure 119. Reset I/O Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) RESET I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc VIH, IO PIN READ AS '1' 3 85 °C 25 °C -40 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 120. Reset I/O Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) RESET I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc VIL, IO PIN READ AS '0' 2.5 85°C 25°C -40°C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 121. Reset I/O Input Pin Hysteresis vs. VCC RESET I/O INPUT PIN HYSTERESIS vs. Vcc 1 0.9 Input Hysteresis (V) 0.8 -40 °C 0.7 0.6 25 °C 0.5 85 °C 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 122. Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) RESET INPUT THRESHOLD VOLTAGE vs. Vcc VIH, IO PIN READ AS '1' 2.5 Threshold (V) 2 1.5 -40 °C 25 °C 85 °C 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny2313/V Figure 123. Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) RESET INPUT THRESHOLD VOLTAGE vs. Vcc VIL, IO PIN READ AS '0' 2.5 Threshold (V) 2 1.5 1 85 °C 25 °C -40 °C 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 5 5.5 Vcc (V) Figure 124. Reset Input Pin Hysteresis vs. VCC RESET INPUT PIN HYSTERESIS vs. Vcc 0.7 -40 °C 0.6 Input Hysteresis (V) 0.5 25 °C 0.4 85 °C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.
BOD Thresholds and Analog Comparator Offset Figure 125. BOD Thresholds vs. Temperature (BOD Level is 4.3V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.3V 4.45 Rising Vcc Thres hol d (V ) 4.4 4.35 Falling Vcc 4.3 4.25 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 80 90 Temperature (C) Figure 126. BOD Thresholds vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 2.7V 2.85 Rising Vcc Threshold (V) 2.8 2.75 Falling Vcc 2.7 2.
ATtiny2313/V Figure 127. BOD Thresholds vs. Temperature (BOD Level is 1.8V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 1.8V 1.88 1.86 Threshold (V) Rising Vcc 1.84 1.82 Falling Vcc 1.8 1.78 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (C) Internal Oscillator Speed Figure 128. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. VCC 0.104 0.103 0.102 -40 °C F RC (M Hz ) 0.101 0.1 25 °C 0.099 0.098 0.097 0.096 85 °C 0.095 1.5 2 2.5 3 3.5 4 4.
Figure 129. Watchdog Oscillator Frequency vs. Temperature WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 0.105 0.104 0.103 F RC (MHz) 0.102 0.101 0.1 1.8 V 0.099 2.7 V 0.098 3.3 V 0.097 4.0 V 5.5 V 5.0 V 4.5 V 0.096 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 130. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8.4 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 8.3 F RC (MHz ) 8.2 8.1 8 7.9 7.8 7.
ATtiny2313/V Figure 131. Calibrated 8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. Vcc 8.4 8.3 85 °C FRC (MHz) 8.2 8.1 25 °C 8 -40 °C 7.9 7.8 7.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 132. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs.
Figure 133. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 4.2 5.5 V 5.0 V 3.3 V 1.8 V 4.15 FRC (MHz) 4.1 4.05 4 3.95 3.9 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 134. Calibrated 4 MHz RC Oscillator Frequency vs. VCC CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. Vcc 4.2 4.15 85 °C FRC (MHz) 4.1 4.05 25 °C 4 -40 °C 3.95 3.9 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny2313/V Figure 135. Calibrated 4 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 7 25 °C 6 F RC (MHz ) 5 4 3 2 1 0 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 OSCCAL VALUE Current Consumption of Peripheral Units Figure 136. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. Vcc 30 -40 °C 85 °C 25 °C 25 Icc (uA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 137. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. Vcc 70 -40 °C 60 25 °C 85 °C Icc (uA) 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 5 5.5 Vcc (V) Figure 138. Programming Current vs. VCC PROGRAMMING CURRENT vs. Vcc 4.5 4 3.5 -40 °C Icc (mA) 3 2.5 25 °C 2 1.5 85 °C 1 0.5 0 1.5 2 2.5 3 3.5 4 4.
ATtiny2313/V Current Consumption in Reset and Reset Pulsewidth Figure 139. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. Vcc 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 0.14 5.5 V 0.12 5.0 V 4.5 V Icc (mA) 0.1 4.0 V 0.08 3.3 V 0.06 2.7 V 0.04 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 140. Reset Supply Current vs.
Figure 141. Minimum Reset Pulse Width vs. VCC MINIMUM RESET PULSE WIDTH vs. Vcc 2500 Pulsewidth (ns) 2000 1500 1000 500 85 °C 25 °C -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny2313/V Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3F (0x5F) SREG I T H S V N Z C 7 0x3E (0x5E) Reserved – – – – – – – – 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 0x3C (0x5C) OCR0B 0x3B (0x5B) GIMSK INT1 INT0 PCIE – – – – – 0x3A (0x5A) EIFR INTF1 INTF0 PCIF – – – – – 61 0x39 (0x59) TIMSK TOIE1 OCIE1A OCIE1B – ICIE1 OCIE0B TOIE0 OCIE0A 78, 109 0x38 (0x58) TIFR TOV1 – ICF1 OCF0
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them.
ATtiny2313/V Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two
Mnemonics Operands Description Operation Flags #Clocks ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..
ATtiny2313/V Ordering Information Speed (MHz)(3) 10 20 Note: Ordering Code Package(1) Operation Range 1.8 - 5.5V ATtiny2313V-10PI ATtiny2313V-10PU(2) ATtiny2313V-10SI ATtiny2313V-10SU(2) ATtiny2313V-10MI ATtiny2313V-10MU(2) 20P3 20P3 20S 20S 20M1 20M1 Industrial (-40°C to 85°C) 2.7 - 5.5V ATtiny2313-20PI ATtiny2313-20PU(2) ATtiny2313-20SI ATtiny2313-20SU(2) ATtiny2313-20MI ATtiny2313-20MU(2) 20P3 20P3 20S 20S 20M1 20M1 Industrial (-40°C to 85°C) Power Supply 1.
Packaging Information 20P3 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E COMMON DIMENSIONS (Unit of Measure = mm) C eC eB Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). MIN NOM MAX A – – 5.334 A1 0.381 – – D 25.493 – 25.984 E 7.620 – 8.255 SYMBOL E1 6.096 – 7.112 B 0.356 – 0.559 B1 1.270 – 1.551 L 2.921 – 3.810 C 0.
ATtiny2313/V 20S C 1 L E H N A1 Top View End View COMMON DIMENSIONS (Unit of Measure = inches) e SYMBOL b A D Side View MIN NOM MAX A 0.0926 0.1043 A1 0.0040 0.0118 NOTE b 0.0130 0.0200 C 0.0091 0.0125 D 0.4961 0.5118 1 2 E 0.2914 0.2992 H 0.3940 0.4190 L 0.0160 0.050 e 4 3 0.050 BSC Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information. 2.
20M1 D 1 Pin 1 ID 2 SIDE VIEW E 3 TOP VIEW A2 D2 A1 A 0.08 1 2 Pin #1 Notch (0.20 R) 3 COMMON DIMENSIONS (Unit of Measure = mm) E2 b L e BOTTOM VIEW SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 – 0.01 0.05 A2 b 0.18 D D2 E2 L 0.23 0.30 4.00 BSC 2.45 2.60 2.75 4.00 BSC 2.45 e Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. NOTE 0.20 REF E Note: C 2.60 2.75 0.50 BSC 0.35 0.40 0.
ATtiny2313/V Errata The revision in this section refers to the revision of the ATtiny2313 device. ATtiny2313 Rev B • • • • Wrong values read after Erase Only operation Parallel Programming does not work Watchdog Timer Interrupt disabled EEPROM can not be written below 1.9 volts 1. Wrong values read after Erase Only operation At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase Only operation may read as programmed (0x00).
Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04 1. 2. 3. 4. 5. Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04 Changes from Rev. 2514E-04/04 to Rev. 2514F-08/04 1. 2. 3. 4. 5. Updated “Features” on page 1. Updated “Pinout ATtiny2313” on page 2. Updated “Ordering Information” on page 215.
ATtiny2313/V Changes from Rev. 2514C-12/03 to Rev. 2514D-03/04 1. 2. 3. 4. 5. 6. 7. 8. 9. Updated Table 2 on page 22. Replaced “Watchdog Timer” on page 38. Added “Maximum Speed vs. VCC” on page 180. “Serial Programming Algorithm” on page 173 updated. Changed mA to µA in preliminary Figure 136 on page 207. “Ordering Information” on page 215 updated. MLF package option removed Package drawing “20P3” on page 216 updated. Updated C-code examples.
ATtiny2313/V 2543H–AVR–02/05
ATtiny2313 Table of Contents Features................................................................................................ 1 Pin Configurations............................................................................... 2 Overview............................................................................................... 2 Block Diagram ...................................................................................................... 3 Pin Descriptions..................................
Interrupts ............................................................................................ 43 Interrupt Vectors in ATtiny2313 .......................................................................... 43 I/O-Ports.............................................................................................. 45 Introduction ......................................................................................................... Ports as General Digital I/O .......................................
ATtiny2313 Examples of Baud Rate Setting........................................................................ 134 Universal Serial Interface – USI...................................................... 138 Overview........................................................................................................... Functional Descriptions .................................................................................... Alternative USI Usage ........................................................
Packaging Information .................................................................... 216 20P3 ................................................................................................................. 216 20S ................................................................................................................... 217 20M1................................................................................................................. 218 Errata ........................................
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