Datasheet

11
ATtiny20 [DATASHEET]
8235ES–AVR–03/2013
SBI A, b Set Bit in I/O Register I/O(A, b) 1 None 1
CBI A, b Clear Bit in I/O Register I/O(A, b) 0 None 1
BST Rr, b Bit Store from Register to T T Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) T None 1
SEC Set Carry C 1C1
CLC Clear Carry C 0 C 1
SEN Set Negative Flag N 1N1
CLN Clear Negative Flag N 0 N 1
SEZ Set Zero Flag Z 1Z1
CLZ Clear Zero Flag Z 0 Z 1
SEI Global Interrupt Enable I 1I1
CLI Global Interrupt Disable I 0 I 1
SES Set Signed Test Flag S 1S1
CLS Clear Signed Test Flag S 0 S 1
SEV Set Two’s Complement Overflow. V 1V1
CLV Clear Two’s Complement Overflow V 0 V 1
SET Set T in SREG T 1T1
CLT Clear T in SREG T 0 T 1
SEH Set Half Carry Flag in SREG H 1H1
CLH Clear Half Carry Flag in SREG H 0 H
1
DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr Copy Register Rd Rr None 1
LDI Rd, K Load Immediate Rd K None 1
LD Rd, X Load Indirect Rd (X) None 1/2
LD Rd, X+ Load Indirect and Post-Increment Rd (X), X X + 1 None 2
LD Rd, - X Load Indirect and Pre-Decrement X X - 1, Rd (X) None 2/3
LD Rd, Y Load Indirect Rd (Y) None 1/2
LD Rd, Y+ Load Indirect and Post-Increment Rd (Y), Y Y + 1 None 2
LD Rd, - Y Load Indirect and Pre-Decrement Y Y - 1, Rd (Y) None 2/3
LD Rd, Z Load Indirect Rd (Z) None 1/2
LD Rd, Z+ Load Indirect and Post-Increment Rd (Z), Z Z+1 None 2
LD Rd, -Z Load Indirect and Pre-Decrement Z Z - 1, Rd (Z) None 2/3
LDS Rd, k Store Direct from SRAM Rd k) None 1
ST X, Rr Store Indirect (X) Rr None 1
ST X+, Rr Store Indirect and Post-Increment (X) Rr, X X + 1 None 1
ST - X, Rr Store Indirect and Pre-Decrement X X - 1, (X) Rr None 2
ST Y, Rr Store Indirect (Y) Rr None 1
ST Y+, Rr Store Indirect and Post-Increment (Y) Rr, Y Y + 1 None 1
ST - Y, Rr Store Indirect and Pre-Decrement Y Y - 1, (Y) Rr None 2
ST Z, Rr Store Indirect (Z) Rr None 1
ST Z+, Rr Store Indirect and Post-Increment. (Z) Rr, Z Z + 1 None 1
ST -Z, Rr Store Indirect and Pre-Decrement Z Z - 1, (Z) Rr None 2
STS k, Rr Store Direct to SRAM (k) Rr None 1
IN Rd, A In from I/O Location Rd I/O (A) None 1
OUT A, Rr Out to I/O Location I/O (A) Rr None 1
PUSH Rr Push Register on Stack STACK Rr None 2
POP Rd Pop Register from Stack Rd STACK None 2
MCU CONTROL INSTRUCTIONS
BREAK Break
(see specific descr. for Break)
None
1
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep) None 1
WDR Watchdog Reset (see specific descr. for WDR) None
1
Mnemonics Operands Description Operation Flags #Clocks