Datasheet

97
7728G–AVR–06/10
ATtiny87/ATtiny167
10.8 Timer/Counter Timing Diagrams
The following figures show the Timer/Counter in synchronous mode, and the timer clock
(clk
T
0) is therefore shown as a clock enable signal. In asynchronous mode, clk
I/O
should be
replaced by the Timer/Counter Oscillator clock. The figures include information on when inter-
rupt flags are set. Figure 10-8 contains timing data for basic Timer/Counter operation. The
figure shows the count sequence close to the MAX value in all modes other than phase correct
PWM mode.
Figure 10-8. Timer/Counter Timing Diagram, no Prescaling
Figure 10-9 shows the same timing data, but with the prescaler enabled.
Figure 10-9. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
Figure 10-10 shows the setting of OCF0A in all modes except CTC mode.
Figure 10-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f
clk_I/O
/8)
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)