Datasheet

89
7728G–AVR–06/10
ATtiny87/ATtiny167
10.2.1 Definitions
The following definitions are used extensively throughout the section:
10.3 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source is selected by the clock select logic which is controlled by the
clock select (CS02:0) bits located in the Timer/Counter control register (TCCR0).The clock
source clk
T
0 is by default equal to the MCU clock, clk
I/O
. When the AS0 bit in the ASSR Regis-
ter is written to logic one, the clock source is taken from the Timer/Counter Oscillator
connected to XTAL1 and XTAL2 or directly from XTAL1. For details on asynchronous opera-
tion, see “Asynchronous Status Register – ASSR” on page 103. For details on clock sources
and prescaler, see “Timer/Counter0 Prescaler” on page 100.
10.4 Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Fig-
ure 10-2 shows a block diagram of the counter and its surrounding environment.
Figure 10-2. Counter Unit Block Diagram
Signal description (internal signals):
count Increment or decrement TCNT0 by 1.
direction Selects between increment and decrement.
clear Clear TCNT0 (set all bits to zero).
clk
T
0 Timer/Counter0 clock.
top Signalizes that TCNT0 has reached maximum value.
bottom Signalizes that TCNT0 has reached minimum value (zero).
BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00).
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP The counter reaches the TOP when it becomes equal to the highest value in
the count sequence. The TOP value can be assigned to be the fixed value
0xFF (MAX) or the value stored in the OCR0A Register. The assignment is
dependent on the mode of operation.
DATA BUS
TCNTn Control Logic
count
TOVn
(Int.Req.)
topbottom
direction
clear
XTAL2
Oscillator
XTAL1
Prescaler
clk
I/O
clk
Tn
clk
TnS