Datasheet

66
7728G–AVR–06/10
ATtiny87/ATtiny167
8.3.7 Pin Change Mask Register 0 – PCMSK0
• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0
Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
Bit 76543210
PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000