Datasheet

7728G–AVR–06/10

ATtiny87/ATtiny167

5.5 Power-down Mode

When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter

Power-down mode. In this mode, the external Oscillator is stopped, while the external inter-

rupts, the USI start condition, and the Watchdog continue operating (if enabled). Only an

External Reset, a Watchdog System Reset, a Watchdog Interrupt, a Brown-out Reset, the USI

start condition interrupt, an external level interrupt on INT0 or INT1, or a pin change interrupt

can wake up the MCU. This sleep mode basically halts all generated clocks, allowing opera-

tion of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the

changed level must be held for some time to wake up the MCU. Refer to Section 8. “External

Interrupts” on page 62 for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs

until the wake-up becomes effective. This allows the clock to restart and become stable after

having been stopped. The wake-up period is defined by the same CKSEL Fuses that define

the Reset Time-out period, as described in Section 4.2 “Clock Sources” on page 25.

5.6 Power-save Mode

When the SM1..0 bits are written to 11, the SLEEP instruction makes the MCU enter

Power-save mode. This mode is identical to Power-down, with one exception:

If Timer/Counter0 is clocked asynchronously, i.e., the AS0 bit in ASSR is set, Timer/Counter0

will run during sleep. The device can wake up from either Timer Overflow or Output Compare

event from Timer/Counter0 if the corresponding Timer/Counter0 interrupt enable bits are set in

TIMSK0, and the global interrupt enable bit in SREG is set.

If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is recom-

mended instead of Power-save mode because the contents of the registers in the

asynchronous timer should be considered undefined after wake-up in Power-save mode if

AS0 is 0.

This sleep mode basically halts all clocks except clk

ASY

, allowing operation only of asynchro-

nous modules, including Timer/Counter0 if clocked asynchronously.

5.7 Power Reduction Register

The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 47,

provides a method to stop the clock to individual peripherals to reduce power consumption.

The current state of the peripheral is frozen and the I/O registers can not be read or written.

Resources used by the peripheral when stopping the clock will remain occupied, hence the

peripheral should in most cases be disabled before stopping the clock. Waking up a module,

which is done by clearing the bit in PRR, puts the module in the same state as before

shutdown.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall

power consumption. In all other sleep modes, the clock is already stopped.