Datasheet

4
7728G–AVR–06/10
ATtiny87/ATtiny167
1.5 Block Diagram
Figure 1-1. Block Diagram
PORT A (8) LIN / UARTPORT B (8)
SPI & USI
Timer/Counter-0
Timer/Counter-1 A/D Conv.
Internal
Voltage
References
Analog Comp.
SRAMFlash
EEPROM
Watchdog
Oscillator
Watchdog
Timer
Oscillator
Circuits /
Clock
Generation
Power
Supervision
POR / BOD &
RESET
VCC
GND
PROGRAM
LOGIC
debugWIRE
AGND
AVCC
DATA BUS
PA[0..7]PB[0..7]
11
RESET
XTAL[1;2]
CPU
2