Datasheet

31
7728G–AVR–06/10
ATtiny87/ATtiny167
Notes: 1. Flash Fuse bits.
2. CLKSELR register bits.
3. Additional delay (+ 4ms) available if RSTDISBL fuse is set.
Note that the System Clock Prescaler can be used to implement run-time changes of the inter-
nal clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on
page 37 for details.
4.2.7 Clock Output Buffer
If not using a crystal oscillator, the device can output the system clock on the CLKO pin. To
enable the output, the CKOUT Fuse or COUT bit of CLKSELR register has to be programmed.
This option is useful when the device clock is needed to drive other circuits on the system.
Note that the clock will not be output during reset and the normal operation of I/O pin will be
overridden when the fuses are programmed. If the System Clock Prescaler is used, it is the
divided system clock that is output.
4.3 Dynamic Clock Switch
4.3.1 Features
The ATtiny87/167 provides a powerful dynamic clock switch circuit that allows users to turn on
and off clocks of the device on the fly. The built-in de-glitching circuitry allows clocks to be
enabled or disabled asynchronously. This enables efficient power management schemes to
be implemented easily and quickly. In a safety application, the dynamic clock switch circuit
allows continuous monitoring of the external clock permitting a fallback scheme in case of
clock failure.
The control of the dynamic clock switch circuit must be supervised by software. This operation
is facilitated by the following features:
• Safe commands, to avoid unintentional commands, a special write procedure must be
followed to change the CLKCSR register bits (See “CLKPR – Clock Prescaler Register” on
page 38.):
• Exclusive action, the actions are controlled by a decoding table (commands) written to the
CLKCSR register. This ensures that only one command operation can be launched at any
time. The main actions of the decoding table are:
–‘Disable Clock Source’,
–‘Enable Clock Source’,
–‘Request Clock Availability’,
–‘Clock Source Switching’,
Table 4-9. Start-up Times for the External Clock Selection
SUT1..0
(1)
CSUT1..0
(2)
Start-up Time from
Power-down/save
Additional Delay from Reset
(Vcc = 5.0V) Recommended Usage
00 6 CK 14CK (+ 4.1 ms
(3)
) BOD enabled
01 6 CK 14CK + 4.1 ms Fast rising power
10 6 CK 14CK + 65 ms Slowly rising power
11 Reserved