Datasheet

7728G–AVR–06/10

ATtiny87/ATtiny167

3. ‘Disable Clock Source’ command remains enabled.

In the Dynamic Clock Switch module, the ‘Disable Clock Source’ command remains run-

ning after disabling the targeted clock source (the clock source is set in the CLKSELR

Problem fix / workaround.

After a ‘Disable Clock Source’ command, reset the CLKCSR register writing 0x80.

Code example:

; Select crystal oscillator

ldi temp1,(0x0F<<CSEL0)

sts CLKSELR, temp1

; Disable clock source (crystal oscillator)

ldi temp2,(1<<CLKCCE)

ldi temp3,(0x01<<CLKC0) ; CSEL = "0001"

sts CLKCSR,temp2 ; Enable CLKCSR register access

sts CLKCSR,temp3 ; (*) Disable crystal oscillator clock

; (*) !!! At this moment, if any other clock source is selected by

CLKSELR,

; this clock source will also stop !!!

; ==> WORKAROUND ...

sts CLKCSR,temp2

4. Comparison between ADC inputs and voltage references.

In the Analog Comparator module, comparing any ADC input (ADC[10..0]) with voltage

references (2.56V, 1.28V, 1.10V, 0.64V or 0.32V) fails.

Regardless, AIN1 input can be compared with the voltage references and any ADC input

can be compared with AIN0 input.

Problem fix / workaround.

Do not use this configuration.

5. Register bits of DIDR1.

ADC8D, ADC9D and ADC10D (Digital Input Disable) initially located at bit 4 up to 6 are

instead located at bit 0 up to 2. These register bits are also in write only mode.

Problem fix / workaround.

Allow for the change in bit locations and the access mode restriction.