Datasheet

251
7728G–AVR–06/10
ATtiny87/ATtiny167
Figure 22-4. Parallel Programming Timing, Loading Sequence with Timing Requirements
(1)
Note: 1. The timing requirements shown in Figure 22-3 (i.e., t
DVXH
, t
XHXL
, and t
XLDX
) also apply to
loading operation.
Figure 22-5. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Timing Requirements
(Note:)
Note: The timing requirements shown in Figure 22-3 (i.e., t
DVXH
, t
XHXL
, and t
XLDX
) also apply to read-
ing operation.
XTAL1
XLXH
t
ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
DATA
AGEL/BS1
XA0
XA1/BS2
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
XTAL1
OE
ADDR0 (Low Byte) DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
DATA
AGEL/BS1
XA0
XA1/BS2
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
t
BVDV
t
OLDV
t
XLOL
t
OHDZ