Datasheet

239
7728G–AVR–06/10
ATtiny87/ATtiny167
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high peri-
ods for the serial clock (SCK) input are defined as follows:
Low
: > 2 CPU clock cycles for f
ck
< 12 MHz, 3 CPU clock cycles for f
ck
>= 12 MHz
Hi
gh: > 2 CPU clock cycles for f
ck
< 12 MHz, 3 CPU clock cycles for f
ck
>= 12 MHz
21.8.1 Serial Programming Algorithm
When writing serial data to the ATtiny87/167, data is clocked on the rising edge of SCK.
When reading data from the ATtiny87/167, data is clocked on the falling edge of SCK. See
Figure 21-7 and Figure 21-8 for timing details.
To program and verify the ATtiny87/167 in the Serial Programming mode, the following
sequence is recommended (see four byte instruction formats in Table 21-15 on page 240):
1. Power-up sequence:
Apply power between Vcc and GND while RESET
and SCK are set to “0”. In some
systems, the programmer can not guarantee that SCK is held low during power-up. In
this case, RESET
must be given a positive pulse of at least two CPU clock cycles
duration after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of syn-
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not,
all four bytes of the instruction must be transmitted. If the 0x53 did not echo back,
give RESET
a positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte
at a time by supplying the 5 LSB of the address and data together with the Load Pro-
gram memory Page instruction. To ensure correct loading of the page, the data low
byte must be loaded before data high byte is applied for a given address. The Pro-
gram memory Page is stored by loading the Write Program memory Page instruction
with the 6 MSB of the address. If polling (RDY/BSY)
is not used, the user must wait at
least t
WD_FLASH
before issuing the next page. (See Table 21-14) Accessing the serial
programming interface before the Flash write operation completes can result in incor-
rect programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the address
and data together with the appropriate Write instruction. An EEPROM memory loca-
tion is first automatically erased before new data is written. If polling (RDY/BSY)
is not
used, the user must wait at least t
WD_EEPROM
before issuing the next byte. (See Table
21-14) In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is
loaded one byte at a time by supplying the 2 LSB of the address and data together
with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is
stored by loading the Write EEPROM Memory Page Instruction with the 6 MSB of the
address. When using EEPROM page access only byte locations loaded with the
Load EEPROM Memory Page instruction is altered. The remaining locations remain
unchanged. If polling (RDY/BSY)
is not used, the used must wait at least t
WD_EEPROM
before issuing the next page (See Table 21-8). In a chip erased device, no 0xFF in
the data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the
content at the selected address at serial output MISO.