Datasheet

229
7728G–AVR–06/10
ATtiny87/ATtiny167
Figure 21-1. Parallel programming
Note: Vcc - 0.3V < AVcc < Vcc + 0.3V, however, AVcc should always be within 4.5 - 5.5V
Table 21-9. Pin Name Mapping
Signal Name in
Programming Mode Pin Name I/O Function
WR
PB0 I Write Pulse (Active low).
XA0 PB1 I XTAL1 Action Bit 0
XA1 / BS2 PB2 I
- XTAL1 Action Bit 1
- Byte Select 2
(“0” selects low byte, “1” selects 2’nd high byte)
PAGEL / BS1 PB3 I
- Program Memory and EEPROM data Page Load
- Byte Select 1
(“0” selects low byte, “1” selects high byte)
PB4 I XTAL1 (Clock input)
OE
PB5 I Output Enable (Active low).
RDY / BSY
PB6 O
0: Device is busy programming,
1: Device is ready for new command.
+12V PB7 I
- Reset (Active low)
- Parallel programming mode (+12V).
DATA PA7-PA0 I/O Bi-directional Data bus (Output when OE
is low).
Vcc
+4.5 - +5.5V
GND
PB0
PB1
PB2
PB3
PA7 - PA0 DATA
RESET / PB7
XTAL1 / PB4
+12 V
XA0
XA1 / BS2
PAGEL / BS1
WR
PB6
RDY / BSY
AVcc
+4.5 - +5.5V
OE
PB5