Datasheet

196
7728G–AVR–06/10
ATtiny87/ATtiny167
Figure 17-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Figure 17-5. ADC Timing Diagram, Single Conversion
Figure 17-6. ADC Timing Diagram, Auto Triggered Conversion
Sign and MSB of Result
LSB of Result
DC Clock
DSC
Sample & Hold
DIF
DCH
DCL
ycle Number
DEN
1 212
13
14 15
16 17
18 19 20 21 22 23
24 25
1 2
First Conversion
Next
Conversion
3
MUX and REFS
Update
MUX
and REFS
Update
Conversion
Complete
1
2 3 4 5 6 7 8
9 10 11 12 13
Sign and MSB of Result
LSB of Result
DC Clock
DSC
DIF
DCH
DCL
ycle Number
12
One Conversion Next Conversion
3
Sample & Hold
MUX and REFS
Update
Conversion
Complete
MUX and REFS
Update
1 2 3 4 5 6 7 8
9
10 11 12 13
Sign and MSB of Result
LSB of Result
DC Clock
igger
ource
DIF
DCH
DCL
ycle Number
12
One Conversion Next Conversion
Conversion
Complete
Prescaler
Reset
DATE
Prescaler
Reset
Sample &
Hold
MUX and REFS
Update