Datasheet

186
7728G–AVR–06/10
ATtiny87/ATtiny167
15.6.8 LIN Identifier Register - LINIDR
• Bits 7:6 - LP[1:0]: Parity
In LIN mode:
LP0 = LID4 ^ LID2 ^ LID1 ^ LID0
LP1 = ! ( LID1 ^ LID3 ^ LID4 ^ LID5 )
In UART mode this field is unused.
• Bits 5:4 - LDL[1:0]: LIN 1.3 Data Length
In LIN 1.3 mode:
– 00 = 2-byte response,
– 01 = 2-byte response,
– 10 = 4-byte response,
– 11 = 8-byte response.
In UART mode this field is unused.
• Bits 3:0 - LID[3:0]: LIN 1.3 Identifier
In LIN 1.3 mode: 4-bit identifier.
In UART mode this field is unused.
• Bits 5:0 - LID[5:0]: LIN 2.1 Identifier
In LIN 2.1 mode: 6-bit identifier (no length transported).
In UART mode this field is unused.
15.6.9 LIN Data Buffer Selection Register - LINSEL
• Bits 7:4 - Reserved Bits
These bits are reserved for future use. For compatibility with future devices, they must be
written to zero when LINSEL is written.
Bit 76 5 4 3210
LP1 LP0
LID5 /
LDL1
LID4 /
LDL0
LID3 LID2 LID1 LID0 LINIDR
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value00 0 0 0000
Bit 76543210
----LAINC
LINDX2 LINDX1 LINDX0 LINSEL
Read/Write - - - - R/W R/W R/W R/W
Initial Value- - - -0000