Datasheet

185
7728G–AVR–06/10
ATtiny87/ATtiny167
• Bits 5:0 - LBT[5:0]: LIN Bit Timing
Gives the number of samples of a bit.
sample-time = (1 /
fclk
i/o
) x (LDIV[11..0] + 1)
Default value: LBT[6:0]=32 — Min. value: LBT[6:0]=8 — Max. value: LBT[6:0]=63
15.6.6 LIN Baud Rate Register - LINBRR
• Bits 15:12 - Reserved Bits
These bits are reserved for future use. For compatibility with future devices, they must be
written to zero when LINBRR is written.
• Bits 11:0 - LDIV[11:0]: Scaling of clk
i/o
Frequency
The LDIV value is used to scale the entering clk
i/o
frequency to achieve appropriate LIN or
UART baud rate.
15.6.7 LIN Data Length Register - LINDLR
• Bits 7:4 - LTXDL[3:0]: LIN Transmit Data Length
In LIN mode, this field gives the number of bytes to be transmitted (clamped to 8 Max).
In UART mode this field is unused.
• Bits 3:0 - LRXDL[3:0]: LIN Receive Data Length
In LIN mode, this field gives the number of bytes to be received (clamped to 8 Max).
In UART mode this field is unused.
Bit 76543210
LDIV7 LDIV6 LDIV5 LDIV4 LDIV3 LDIV2 LDIV1 LDIV0 LINBRRL
----LDIV11LDIV10LDIV9LDIV8LINBRRH
Bit 151413121110 9 8
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
LTXDL3 LTXDL2 LTXDL1 LTXDL0 LRXDL3 LRXDL2 LRXDL1 LRXDL0 LINDLR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000