Datasheet

183
7728G–AVR–06/10
ATtiny87/ATtiny167
• Bit 0 - LRXOK: Receive Performed Interrupt
This bit generates an interrupt if its respective enable bit - LENRXOK - is set in
LINENIR.
– 0 = No Rx
– 1 = Rx Response complete.
The user clears this bit by writing 1, in order to reset this interrupt.
In UART mode, this bit is also cleared by reading LINDAT.
15.6.3 LIN Enable Interrupt Register - LINENIR
• Bits 7:4 - Reserved Bits
These bits are reserved for future use. For compatibility with future devices, they must be
written to zero when LINENIR is written.
• Bit 3 - LENERR: Enable Error Interrupt
– 0 = Error interrupt masked,
– 1 = Error interrupt enabled.
• Bit 2 - LENIDOK: Enable Identifier Interrupt
– 0 = Identifier interrupt masked,
– 1 = Identifier interrupt enabled.
• Bit 1 - LENTXOK: Enable Transmit Performed Interrupt
– 0 = Transmit performed interrupt masked,
– 1 = Transmit performed interrupt enabled.
• Bit 0 - LENRXOK: Enable Receive Performed Interrupt
– 0 = Receive performed interrupt masked,
– 1 = Receive performed interrupt enabled.
15.6.4 LIN Error Register - LINERR
• Bit 7 - LABORT: Abort Flag
– 0 = No warning,
– 1 = LIN abort command occurred.
This bit is cleared when LERR bit in LINSIR is cleared.
Bit 7654 3 2 1 0
- - - - LENERR LENIDOK LENTXOK LENRXOK LINENIR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
LABORT LTOERR LOVERR LFERR LSERR LPERR LCERR LBERR LINERR
Read/WriteRRRRRRRR
Initial Value00000000