Datasheet

140
7728G–AVR–06/10
ATtiny87/ATtiny167
13. SPI - Serial Peripheral Interface
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between
the ATtiny87/167 and peripheral devices or between several AVR devices. The ATtiny87/167
SPI includes the following features:
13.1 Features
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
Figure 13-1. SPI Block Diagram
(1)
Note: 1. Refer to Figure 1.6 on page 5, and Table 9-3 on page 76 for SPI pin placement.
SPI2X
SPI2X
DIVIDER
/2/4/8/16/32/64/128
clk
IO