Datasheet

136
7728G–AVR–06/10
ATtiny87/ATtiny167
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
12.11.3 Timer/Counter1 Control Register C – TCCR1C
• Bit 7 – FOC1A: Force Output Compare for Channel A
• Bit 6 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode.
However, for ensuring compatibility with future devices, these bits must be set to zero when
TCCR1A is written when operating in a PWM mode. When writing a logical one to the
FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit.
The OC1nx output is changed according to its COM1A/B1:0 and OC1nx bits setting. Note that
the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the
COM1A/B1:0 bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer
on Compare match (CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
12.11.4 Timer/Counter1 Control Register D – TCCR1D
• Bit 7:4 – OC1Bi: Output Compare Pin Enable for Channel B
The OC1Bi bits enable the Output Compare pins of Channel B as shown in Figure 12-6 on
page 122.
• Bit 3:0 – OC1Ai: Output Compare Pin Enable for Channel A
The OC1Ai bits enable the Output Compare pins of Channel A as shown in Figure 12-6 on
page 122.
Bit 7 6 5 4 3 2 1 0
FOC1A FOC1B – – – – – – TCCR1C
Read/Write R/W R/W R/W R R R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OC1BX OC1BW OC1BV OC1BU OC1AX OC1AW OC1AV OC1AU TCCR1D
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0