Datasheet

117
7728G–AVR–06/10
ATtiny87/ATtiny167
The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected
by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.
12.6 Input Capture Unit
The Timer/Counter incorporates an Input Capture unit that can capture external events and
give them a time-stamp indicating time of occurrence. The external signal indicating an event,
or multiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator
unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features
of the signal applied. Alternatively the time-stamps can be used for creating a log of the
events.
The Input Capture unit is illustrated by the block diagram shown in Figure 12-3. The elements
of the block diagram that are not directly a part of the Input Capture unit are gray shaded.
Figure 12-3. Input Capture Unit Block Diagram
When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alterna-
tively on the Analog Comparator output (ACO), and this change confirms to the setting of the
edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the
counter (TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag
(ICF1) is set at the same system clock as the TCNT1 value is copied into ICR1 Register. If
enabled (ICIE1 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF1
flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 flag can be
cleared by software by writing a logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low
byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is cop-
ied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location
it will access the TEMP Register.
The ICR1 Register can only be written when using a Waveform Generation mode that utilizes
the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera-
tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1
WRITE
ICRn (16-bit Register)
ICRnH (8-bit)
TEMP (8-bit)
DATA BUS (8-bit)
ICRnL (8-bit)
TCNTn
(16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
ICF1n (Int.Req.)
Noise
Canceler
Edge
Detector
ACIC ICNCn ICESn
ICPn
Analog
Comparator
ACO