Datasheet

109
7728G–AVR–06/10
ATtiny87/ATtiny167
11.2 Timer/Counter1 Prescalers Register Description
11.2.1 General Timer/Counter Control Register – GTCCR
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode,
the value that is written to the PSR0 and PSR1 bits is kept, hence keeping the corresponding
prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are
halted and can be configured to the same value without the risk of one of them advancing dur-
ing configuration. When the TSM bit is written to zero, the PSR0 and PSR1 bits are cleared by
hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSR1: Prescaler Reset Timer/Counter1
When this bit is one, Timer/Counter1 prescaler will be reset. This bit is normally cleared imme-
diately by hardware, except if the TSM bit is set.
Bit 7 6 5 4 3 2 1 0
TSM
– – – – – PSR0 PSR1 GTCCR
Read/Write R R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0