Datasheet

108
7728G–AVR–06/10
ATtiny87/ATtiny167
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock
cycles from an edge has been applied to the T1 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is
generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the
system clock frequency (f
ExtClk
<f
clk_I/O
/2) given a 50/50 % duty cycle. Since the edge detec-
tor uses sampling, the maximum frequency of an external clock it can detect is half the
sampling frequency (Nyquist sampling theorem). However, due to variation of the system
clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capaci-
tors) tolerances, it is recommended that maximum frequency of an external clock source is
less than f
clk_I/O
/2.5.
An external clock source can not be prescaled.
Figure 11-2. Prescaler for Timer/Counter1
(1)
Note: 1. The synchronization logic on the input pin (T1) is shown in Figure 11-1.
10-BIT T/C PRESCALER
CK/8
CK/64
CK/256
CK/1024
clk
Tn
TIMER/COUNTERn CLOCK SOURCE
0
CSn2
CSn0
CLK
I/O
CSn1
PSRn
Tn
Clear
Synchronization