Datasheet

102
7728G–AVR–06/10
ATtiny87/ATtiny167
• Bit 6, 3 – WGM01:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used, see Table 10-4. Modes of
operation supported by the Timer/Counter unit are: Normal mode (Counter), Clear Timer on
Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (See
”Modes of Operation” on page 92.).
Notes: 1. MAX = 0xFF,
2. BOTTOM = 0x00.
10.11.1 Timer/Counter0 Control Register B – TCCR0B
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A
bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0A out-
put is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is
implemented as a strobe. Therefore it is the value present in the COM0A1:0 bits that deter-
mines the effect of the forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6:3 – Res: Reserved Bits
These bits are reserved in the ATtiny87/167 and will always read as zero.
• Bit 2:0 – CS02:0: Clock Select
Table 10-4. Waveform Generation Mode Bit Description
Mode
WGM01
(CTC0)
WGM00
(PWM0)
Timer/Counter
Mode of Operation TOP
Update of
OCR0A at
TOV0 Flag
Set on
(1)(2)
0 0 0 Normal 0xFF Immediate MAX
1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM
2 1 0 CTC OCR0A Immediate MAX
3 1 1 Fast PWM 0xFF TOP MAX
Bit 76 5 4 3210
FOC0A – – – – CS02 CS01 CS00 TCCR0B
Read/Write W R R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0