Datasheet

100
7728G–AVR–06/10
ATtiny87/ATtiny167
10.10 Timer/Counter0 Prescaler
Figure 10-12. Prescaler for Timer/Counter0
The clock source for Timer/Counter0 is named clk
T
0
S
. clk
T
0
S
is by default connected to the
main system I/O clock clk
IO
. By setting the AS0 bit in ASSR, Timer/Counter0 is asynchro-
nously clocked from the XTAL oscillator or XTAL1 pin. This enables use of Timer/Counter0 as
a Real Time Counter (RTC).
A crystal can then be connected between the XTAL1 and XTAL2 pins to serve as an indepen-
dent clock source for Timer/Counter0.
A external clock can also be used using XTAL1 as input. Setting AS0 and EXCLK enables this
configuration.
For Timer/Counter0, the possible prescaled selections are: clk
T
0
S
/8, clk
T
0
S
/32, clk
T
0
S
/64,
clk
T
0
S
/128, clk
T
0
S
/256, and clk
T
0
S
/1024. Additionally, clk
T
0
S
as well as 0 (stop) may be
selected. Setting the PSR0 bit in GTCCR resets the prescaler. This allows the user to operate
with a predictable prescaler.
10.11 8-bit Timer/Counter Register Description
• Timer/Counter0 Control Register A – TCCR0A
• Bit 7:6 – COM0A1:0: Compare Match Output Mode A
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is con-
nected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0A
pin must be set in order to enable the output driver.
10-BIT T/C PRESCALER
TIMER/COUNTERn CLOCK SOURCE
clk
I/O
clk
TnS
ASn
CSn0
CSn1
CSn2
clk
TnS
/8
clk
TnS
/64
clk
TnS
/128
clk
TnS
/1024
clk
TnS
/256
clk
TnS
/32
0
PSRn
Clear
clk
Tn
0
1
XTAL2
EXCLK
0
1
Oscillator
XTAL1
Bit 76 5 4 3210
COM0A1 COM0A0 – – – – WGM01 WGM00 TCCR0A
Read/Write R/W R/W R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0