Features • High Performance, Low Power Atmel AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • – 123 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Non-volatile Program and Data Memories – 8K/16K Byte of In-System Programmable (ISP) Program Memory Flash Endurance: 10,000 Write/Erase Cycles – 512 Bytes In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – 512 Bytes Internal SRAM – Programmin
1. Description 1.1 Comparison Between ATtiny87 and ATtiny167 ATtiny87 and ATtiny167 are hardware and software compatible. They differ only in memory sizes as shown in Table 1-1. Table 1-1. 1.
ATtiny87/ATtiny167 1.3 Automotive Quality Grade The ATtiny87/167 have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949. This data sheet contains limit values extracted from the results of extensive characterization (temperature and voltage). The quality and reliability of the ATtiny87/167 have been verified during regular product qualification as per AEC-Q100 grade 1.
Block Diagram Block Diagram GND Figure 1-1. VCC 1.5 Watchdog Timer Watchdog Oscillator Oscillator Circuits / Clock Generation Power Supervision POR / BOD & RESET debugWIRE Flash SRAM PROGRAM LOGIC CPU EEPROM AVCC AGND Timer/Counter-0 A/D Conv. Analog Comp. Internal Voltage References DATABUS Timer/Counter-1 SPI & USI 2 11 PORT B (8) PORT A (8) LIN / UART RESET XTAL[1;2] PB[0..7] 4 PA[0..
ATtiny87/ATtiny167 Pin Configuration Pinout ATtiny87/167 - SOIC20 & TSSOP20 (RXLIN / RXD / ADC0 / PCINT0) PA0 (TXLIN / TXD / ADC1 / PCINT1) PA1 (MISO / DO / OC0A / ADC2 / PCINT2) PA2 (INT1 / ISRC / ADC3 / PCINT3) PA3 AVCC AGND (MOSI / SDA / DI / ICP1 / ADC4 / PCINT4) PA4 (SCK / SCL / USCK / T1 / ADC5 / PCINT5) PA5 (SS / AIN0 / ADC6 / PCINT6) PA6 (AREF / XREF / AIN1 / ADC7 / PCINT7) PA7 PB0 (PCINT8 / OC1AU / DI / SDA) PB1 (PCINT9 / OC1BU / DO) PB2 (PCINT10 / OC1AV / USCK / SCL) PB3 (PCINT11 / OC1BV) GND VCC
1.7 1.7.1 Pin Description Vcc Supply voltage. 1.7.2 GND Ground. 1.7.3 AVcc Analog supply voltage. 1.7.4 AGND Analog ground. 1.7.5 Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated.
ATtiny87/ATtiny167 2. AVR CPU Core 2.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 2-1.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register.
ATtiny87/ATtiny167 2.3.1 SREG – AVR Status Register The AVR Status Register – SREG – is defined as: Bit 7 6 5 4 3 2 1 0 I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
2.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATtiny87/ATtiny167 Figure 2-3. The X-, Y-, and Z-registers 15 X-register XH XL 7 0 R27 (0x1B) YH YL 7 0 R29 (0x1D) Z-register 0 R26 (0x1A) 15 Y-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 0 7 R31 (0x1F) 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 2.
2.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 2-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept.
ATtiny87/ATtiny167 2.7.1 Interrupt behavior When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set Global Interrupt Enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 2.7.
ATtiny87/ATtiny167 3. AVR Memories This section describes the different memories in the ATtiny87/167. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny87/167 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. Table 3-1. Memory Mapping.
Timing diagrams for instruction fetch and execution are presented in Section 2.6 “Instruction Execution Timing” on page 12. Figure 3-1. Program Memory Map Program Memory 0x0000 Flash end 3.2 SRAM Data Memory Figure 3-2 shows how the ATtiny87/167 SRAM Memory is organized. The ATtiny87/167 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions.
ATtiny87/ATtiny167 Figure 3-2. Data Memory Map Data Memory 32 Registers 64 I/O Registers 160 Ext I/O Reg. 0x0000 - 0x001F 0x0020 - 0x005F 0x0060 - 0x00FF ISRAM start Internal SRAM (ISRAM size) ISRAM end 3.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 3-3. Figure 3-3.
3.3.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in Table 3-2. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, Vcc is likely to rise or fall slowly on Power-up/down.
ATtiny87/ATtiny167 The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in “OSCCAL – Oscillator Calibration Register” on page 37. The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
ATtiny87/ATtiny167 Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low Vcc reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 3.
• Bit 7:1 – Reserved Bits These bits are reserved for future use and will always read as 0 in ATtiny87/167. • Bits 8:0 – EEAR8:0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL – specifies the high EEPROM address in the EEPROM space (see “E2 size” in Table 3-1 on page 15). The EEPROM data bytes are addressed linearly between 0 and “E2 size”. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. Note: 3.5.
ATtiny87/ATtiny167 • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant interrupt when Non-volatile memory is ready for programming. • Bit 2 – EEMPE: EEPROM Master Program Enable The EEMPE bit determines whether writing EEPE to one will have effect or not.
4. System Clock and Clock Options The ATtiny87/167 provides a large number of clock sources. They can be divided into two categories: internal and external. Some external clock sources can be shared with the asynchronous timer. After reset, the clock source is determined by the CKSEL Fuses. Once the device is running, software clock switching is possible to any other clock sources. Hardware controls are provided for clock switching management but some specific procedures must be observed.
ATtiny87/ATtiny167 4.1.1 CPU Clock – clkCPU The CPU clock is routed to parts of the system concerned with the AVR core operation. Examples of such modules are the General Purpose Register File, the Status Register and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. 4.1.2 I/O Clock – clkI/O The I/O clock is used by the majority of the I/O modules, like synchronous Timer/Counter.
The various choices for each clocking option are given in the following sections. When the CPU wakes up from Power-down or Power-save, or when a new clock source is enabled by the dynamic clock switch circuit, the selected clock source is used to time the start-up, ensuring stable oscillator operation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level before commencing normal operation.
ATtiny87/ATtiny167 Table 4-3. Notes: Internal Calibrated RC Oscillator Operating Modes(1) Frequency Range(2) (MHz) CKSEL3..0(3)(4) CSEL3..0(5) 7.6 - 8.4 0010 1. If 8 MHz frequency exceeds the specification of the device (depends on Vcc), the CKDIV8 fuse can be programmed in order to divide the internal frequency by 8. 2. The frequency ranges are guideline values. 3. The device is shipped with this CKSEL = “0010”. 4. Flash Fuse bits. 5. CLKSELR register bits.
4.2.4 Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 4-2. Either a quartz crystal or a ceramic resonator may be used. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment.
ATtiny87/ATtiny167 The CKSEL0 Fuse together with the SUT1..0 Fuses or CSEL0 together with CSUT1..0 field select the start-up times as shown in Table 4-7. Table 4-7. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0(1) CSEL0(2) SUT1..0(1) CSUT1..0(2) Start-up Time from Power-down/save Additional Delay from Reset (Vcc = 5.0V) 0 00 258 CK(3) 14CK + 4.
Figure 4-3. Low-frequency Crystal Oscillator Connections C1=12-22 pF XTAL2 32.768 KHz XTAL1 C2=12-22 pF GND 12-22 pF capacitors may be necessary if parasitic impedance (pads, wires & PCB) is very low. When this oscillator is selected, start-up times are determined by the SUT fuses or by CSUT field as shown in Table 4-8. Table 4-8. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection (1) SUT1..0 CSUT1..0(2) Start-up Time from Power-down/save Additional Delay from Reset (Vcc = 5.
ATtiny87/ATtiny167 Table 4-9. Start-up Times for the External Clock Selection (1) SUT1..0 CSUT1..0(2) Start-up Time from Power-down/save Additional Delay from Reset (Vcc = 5.0V) 00 6 CK 14CK (+ 4.1 ms(3)) 01 6 CK 14CK + 4.1 ms Fast rising power 10 6 CK 14CK + 65 ms Slowly rising power 11 Notes: Recommended Usage BOD enabled Reserved 1. Flash Fuse bits. 2. CLKSELR register bits. 3. Additional delay (+ 4ms) available if RSTDISBL fuse is set.
– ‘Recover System Clock Source’, – ‘Enable Watchdog in Automatic Reload Mode’. • Command status return. The ‘Request Clock Availability ’ command returns status via the CLKRDY bit in the CLKCSR register. The ‘Recover System Clock Source ’ command returns a code of the current clock source in the CLKSELR register. This information is used in the supervisory software routines as shown in Section 4.3.7 on page 33. 4.3.2 CLKSELR Register 4.3.2.
ATtiny87/ATtiny167 Clock Source’ command. This will indicate via the CLKRDY bit in the CLKCSR register that a valid clock source is available and operational. The ‘Disable Clock Source’ command disables the clock source indicated by the settings of CLKSELR register (only CSEL3..0). If the clock source indicated is currently the one that is used to drive the system clock, the command is not executed.
It is strongly recommended to run this sequence only once the interrupts have been disabled. The user (code) is responsible for the correct implementation of the clock switching sequence. Here is a “light” C-code that describes such a sequence of commands.
ATtiny87/ATtiny167 In the first domain, the user (code) can easily check the validity of the clock(s) (See “COUT Command” on page 33.). In the second domain, the lack of a clock results in the code not running. Thus, the presence of the system clock needs to be monitored by hardware. Using the on-chip watchdog allows this monitoring. Normally, the watchdog reloading is performed only if the code reaches some specific software labels, reaching these labels proves that the system clock is running.
Here is a “light” C-code of a clock switching function using automatic clock monitoring.
ATtiny87/ATtiny167 4.4 4.4.1 System Clock Prescaler Features The ATtiny87/167 system clock can be divided by setting the Clock Prescaler Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH are divided by a factor as shown in Table 4-10 on page 39. 4.4.
the range. Incrementing CAL6..0 by 1 will give a frequency increment of less than 2% in the frequency range 7.3 - 8.1 MHz. 4.5.2 CLKPR – Clock Prescaler Register Bit 7 6 5 4 3 2 1 0 CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 CLKPR See Bit Description • Bit 7 – CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits.
ATtiny87/ATtiny167 Table 4-10. 4.5.
start-up time, the clock frequency and, of course, if the clock is alive. The user’s code has to differentiate between ‘no_clock_signal’ and ‘clock_signal_not_yet_available’ condition. • Bits 3:0 – CLKC3:0: Clock Control Bits 3 - 0 These bits define the command to provide to the ‘Clock Switch’ module. The special write procedure must be followed to change the CLKC3..0 bits (See ”Bit 7 – CLKCCE: Clock Control Change Enable” on page 39.). 1.
ATtiny87/ATtiny167 • Bits 5:4 – CSUT1:0: Clock Start-up Time CSUT bits are initialized with the values of SUT Fuse bits. In case of ‘Enable/Disable Clock Source’ command, CSUT field provides the code of the clock start-up time. Refer to subdivisions of Section 4.2 “Clock Sources” on page 25 for code of clock start-up times. In case of ‘Recover System Clock Source’ command, CSUT field is not affected (no recovering of SUT code).
5. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes. See “BOD Disable” on page 43 for more details. 5.
ATtiny87/ATtiny167 5.2 BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, Table 21-3 on page 226, the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible to disable the BOD by software for some of the sleep modes, see Table 5-1. The sleep mode power consumption will then be at the same level as when BOD is globally disabled by fuses.
5.5 Power-down Mode When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the USI start condition, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog System Reset, a Watchdog Interrupt, a Brown-out Reset, the USI start condition interrupt, an external level interrupt on INT0 or INT1, or a pin change interrupt can wake up the MCU.
ATtiny87/ATtiny167 5.8 Minimizing Power Consumption There are several possibilities to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.
5.8.6 Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to Section 6.3 “Watchdog Timer” on page 53 for details on how to configure the Watchdog Timer. 5.8.
ATtiny87/ATtiny167 Table 5-2. Sleep Mode Select SM1 SM0 Sleep Mode 0 0 Idle 0 1 ADC Noise Reduction 1 0 Power-down 1 1 Power-save • Bit 0 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.
• Bit5 - PRLIN: Power Reduction LIN / UART controller Writing a logic one to this bit shuts down the LIN by stopping the clock to the module. When waking up the LIN again, the LIN should be re initialized to ensure proper operation. • Bit 4 - PRSPI: Power Reduction Serial Peripheral Interface If using debugWIRE On-chip Debug System, this bit should not be written to one. Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module.
ATtiny87/ATtiny167 6. System Control and Reset 6.1 6.1.1 Reset Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be an RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
Figure 6-1. Reset Circuit DATA BUS PORF BORF EXTRF WDRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor RSTDISBL Spike Filter Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 6.1.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 22-4 on page 246. The POR is activated whenever Vcc is below the detection level.
ATtiny87/ATtiny167 Figure 6-3. MCU Start-up, RESET Extended Externally VCCRR VCC VPOR RESET VRST tTOUT TIME-OUT INTERNAL RESET 6.1.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 22-3 on page 246) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
Figure 6-5. Brown-out Reset During Operation VCC VBOT+ VBOT- RESET tTOUT TIME-OUT INTERNAL RESET 6.1.6 Watchdog System Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 53 for details on operation of the Watchdog Timer. Figure 6-6. Watchdog System Reset During Operation CC CK 6.1.
ATtiny87/ATtiny167 • Bit 1 – EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 0 – PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR as early as possible in the program.
Figure 6-7. Watchdog Timer WATCHDOG PRESCALER OSC / 2K OSC / 4K OSC / 8K OSC / 16K OSC / 32K OSC / 64K OSC / 128K OSC / 256K OSC / 512K OSC / 1024K ~128 KHz OSCILLATOR WATCHDOG RESET WDP0 WDP1 WDP2 WDP3 CLOCK MONITORING WDE MCU RESET WDIF INTERRUPT WDIE The WDT gives an interrupt or a system reset when the counter reaches a given time-out value.
ATtiny87/ATtiny167 The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.
The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example(1) WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence lds r16, WDTCR ori r16, (1<
ATtiny87/ATtiny167 6.3.3 Watchdog Timer Control Register - WDTCR Bit 7 6 5 4 3 2 1 0 WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 X 0 0 0 WDTCR • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector.
• Bit 3 - WDE: Watchdog System Reset Enable WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. • Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0 The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running.
ATtiny87/ATtiny167 7. Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny87/167. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. 7.1 Interrupt Vectors in ATtiny87/167 Table 7-1. Reset and Interrupt Vectors in ATtiny87/167 Program Address Vector Nb.
7.
ATtiny87/ATtiny167 7.
8. External Interrupts 8.1 Overview The External Interrupts are triggered by the INT1..0 pins or any of the PCINT15..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT1..0 or PCINT15..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCINT1 will trigger if any enabled PCINT15..8 pin toggles. The pin change interrupt PCINT0 will trigger if any enabled PCINT7..0 pin toggles.
ATtiny87/ATtiny167 8.3 8.3.1 External Interrupts Register Description External Interrupt Control Register A – EICRA The External Interrupt Control Register A contains control bits for interrupt sense control. Bit 7 6 5 4 3 2 1 0 – – – – ISC11 ISC10 ISC01 ISC00 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EICRA • Bit 7..4 – Res: Reserved Bits These bits are unused bits in the ATtiny87/167, and will always read as zero.
• Bit 1 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the External Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output.
ATtiny87/ATtiny167 • Bit 1 - PCIE1: Pin Change Interrupt Enable 1 When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register.
8.3.7 Pin Change Mask Register 0 – PCMSK0 Bit 7 6 5 4 3 2 1 0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK0 • Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0 Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..
ATtiny87/ATtiny167 9. I/O-Ports 9.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
9.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 9-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 9-2. General Digital I/O(Note:) PUD Q D DDxn Q CLR WDx RESET 1 D 0 PORTxn Q CLR WPx RESET DATA BUS Q Pxn RDx WRx SLEEP RRx SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL clkI/O : I/O CLOCK Note: 9.2.
ATtiny87/ATtiny167 9.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI assembler instruction can be used to toggle one single bit in a port. 9.2.3 Break-Before-Make Switching In the Break-Before-Make mode when switching the DDRxn bit from input to output an immediate tri-state period lasting one system clock cycle is introduced as indicated in Figure 9-3.
Table 9-1 summarizes the control signals for the pin value. Table 9-1. DDxn PORTxn PUD (in MCUCR) (1) I/O Pull-up 0 0 X Input No Tri-state (Hi-Z) 0 1 0 Input Yes Pxn will source current if ext. pulled low. 0 1 1 Input No Tri-state (Hi-Z) 1 0 X Output No Output Low (Sink) 1 1 X Output No Output High (Source) Note: 9.2.5 Port Pin Configurations Comment 1. Or port-wise PUDx bit in PORTCR register.
ATtiny87/ATtiny167 Figure 9-5. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK r16 INSTRUCTIONS 0xFF out PORTx, r16 nop in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7.
9.2.6 Digital Input Enable and Sleep Modes As shown in Figure 9-2, the digital input signal can be clamped to ground at the input of the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down or Power-save mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to Vcc/2. SLEEP is overridden for port pins enabled as external interrupt pins.
ATtiny87/ATtiny167 Figure 9-6.
Table 9-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 9-6 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 9-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
ATtiny87/ATtiny167 9.3.1 MCU Control Register – MCUCR Bit 7 6 5 4 3 2 1 0 – BODS BODSE PUD – – – – Read/Write R R/W R/W R/W R R R R Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0, 1). See “Configuring the Pin” on page 68 for more details about this feature. 9.3.
9.3.3 Alternate Functions of Port A The Port A pins with alternate functions are shown in Table 9-3. Table 9-3.
ATtiny87/ATtiny167 The alternate pin configuration is as follows: • PCINT7/ADC7/AIN1/XREF/AREF – Port A, Bit7 PCINT7: Pin Change Interrupt, source 7. ADC7: Analog to Digital Converter, channel 7. AIN1: Analog Comparator Positive Input. This pin is directly connected to the positive input of the Analog Comparator. XREF: Internal Voltage Reference Output. The internal voltage reference 2.56V or 1.1V is output when XREFEN is set and if either 2.56V or 1.1V is used as reference for ADC conversion.
Master, the data direction of this pin is controlled by DDA3. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTA3 bit. • PCINT3/ADC3/ISRC/INT1 – Port A, Bit 3 PCINT3: Pin Change Interrupt, source 3. ADC3: Analog to Digital Converter, channel 3. ISCR: Current Source Output pin. While current is sourced by the Current Source module, the user can use the Analog to Digital Converter channel 4 (ADC4) to measure the pin voltage. INT1: External Interrupt, source 1.
ATtiny87/ATtiny167 Table 9-4. Overriding Signals for Alternate Functions in PA7..
Table 9-5. Overriding Signals for Alternate Functions in PA3..
ATtiny87/ATtiny167 9.3.4 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 9-6. Table 9-6.
RESET: Reset input pin. When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O pin, and the part will have to rely on Power-on Reset and Brown-out Reset as its reset sources. When the RSTDISBL Fuse is unprogrammed, the reset circuitry is connected to the pin, and the pin can not be used as an I/O pin. If PB7 is used as a reset pin, DDB7, PORTB7 and PINB7 will all read 0.
ATtiny87/ATtiny167 • PCINT10/OC1AV/USCK/SCL – Port B, Bit 2 PCINT10: Pin Change Interrupt, source 10. OC1AV: Output Compare and PWM Output A-V for Timer/Counter1. The PB2 pin has to be configured as an output (DDB2 set (one)) to serve this function. The OC1AV pin is also the output pin for the PWM mode timer function (c.f. OC1AV bit of TCCR1D register). USCK: Three-wire Mode USI Clock Input. SCL: Two-wire Mode USI Clock Input. • PCINT9/OC1BU/DO – Port B, Bit 1 PCINT9: Pin Change Interrupt, source 9.
Table 9-7 and Table 9-8 relate the alternate functions of Port B to the overriding signals shown in Figure 9-6 on page 73. Table 9-7. Signal Name 84 Overriding Signals for Alternate Functions in PB7..
ATtiny87/ATtiny167 Table 9-8. Overriding Signals for Alternate Functions in PB3..
9.4 9.4.1 Register Description for I/O Ports Port A Data Register – PORTA Bit 9.4.2 7 6 5 4 3 2 1 0 PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Port A Data Direction Register – DDRA Bit 9.4.
ATtiny87/ATtiny167 10. 8-bit Timer/Counter0 and Asynchronous Operation Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: 10.1 Features • • • • • • • 10.2 Single Channel Counter Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Frequency Generator 10-bit Clock Prescaler Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A) Allows Clocking from External Crystal (i.e.
Figure 10-1. 8-bit Timer/Counter0 Block Diagram TCCRnx count TOVn (Int.Req.) clear Control Logic direction clkTn XTAL2 BOTTOM TOP Oscillator Prescaler XTAL1 Timer/Counter TCNTn =0 = 0xFF DATA BUS OCnx (Int.Req.) Waveform Generation = clk I/O OCnx OCRnx Synchronized Status flags clk I/O Synchronization Unit clk ASY Status flags ASSRn asynchronous mode select (ASn) The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Interrupt request (shorten as Int.Req.
ATtiny87/ATtiny167 10.2.1 Definitions The following definitions are used extensively throughout the section: 10.3 BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
ATtiny87/ATtiny167 The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0A Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
Figure 10-4. Compare Match Output Logic COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O 10.6.1 Compare Output Function The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
ATtiny87/ATtiny167 For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 97. 10.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00).
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC0A = fclk_I/O/2 when OCR0A is set to zero (0x00).
ATtiny87/ATtiny167 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0A1:0 to three (See Table 10-2 on page 101).
Figure 10-7. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin.
ATtiny87/ATtiny167 10.8 Timer/Counter Timing Diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT0) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when interrupt flags are set. Figure 10-8 contains timing data for basic Timer/Counter operation.
Figure 10-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Figure 10-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP OCRnx OCFnx 10.9 Asynchronous Operation of Timer/Counter0 When Timer/Counter0 operates asynchronously, some considerations must be taken.
ATtiny87/ATtiny167 TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering Power-save mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: a. Write a value to TCCR0A, TCNT0, or OCR0A. b. Wait until the corresponding Update Busy flag in ASSR returns to zero. c.
10.10 Timer/Counter0 Prescaler Figure 10-12. Prescaler for Timer/Counter0 clkTnS clkTnS/8 1 XTAL1 1 clkTnS/1024 10-BIT T/C PRESCALER Clear clkTnS/256 0 clkTnS/128 0 clkTnS/64 Oscillator clkTnS/32 clkI/O XTAL2 ASn EXCLK 0 PSRn CSn0 CSn1 CSn2 TIMER/COUNTERn CLOCK SOURCE clkTn The clock source for Timer/Counter0 is named clkT0S. clkT0S is by default connected to the main system I/O clock clkIO.
ATtiny87/ATtiny167 When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM01:0 bit setting. Table 10-1 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM). Table 10-1. Compare Output Mode, non-PWM Mode COM0A1 COM0A0 Description 0 0 Normal port operation, OC0A disconnected. 0 1 Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match. 1 1 Set OC0A on Compare Match.
• Bit 6, 3 – WGM01:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used, see Table 10-4. Modes of operation supported by the Timer/Counter unit are: Normal mode (Counter), Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (See ”Modes of Operation” on page 92.). Table 10-4.
ATtiny87/ATtiny167 The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 10-5. Table 10-5. 10.11.2 Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped).
• Bit 5 – AS0: Asynchronous Timer/Counter0 When AS0 is written to zero, Timer/Counter0 is clocked from the I/O clock, clkI/O and the Timer/Counter0 acts as a synchronous peripheral. When AS0 is written to one, Timer/Counter0 is clocked from the low-frequency crystal oscillator (See ”Low-frequency Crystal Oscillator” on page 29.) or from external clock on XTAL1 pin (See ”External Clock” on page 30.) depending on EXCLK setting.
ATtiny87/ATtiny167 10.11.5 Timer/Counter0 Interrupt Mask Register – TIMSK0 Bit 7 6 5 4 3 2 1 0 – – – – – – OCIE0A TOIE0 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK0 • Bit 7:2 – Res: Reserved Bits These bits are reserved in the ATtiny87/167 and will always read as zero.
10.11.7 General Timer/Counter Control Register – GTCCR Bit 7 6 5 4 3 2 1 0 TSM – – – – – PSR0 PSR1 Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR • Bit 1 – PSR0: Prescaler Reset Timer/Counter0 When this bit is one, the Timer/Counter0 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter0 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset.
ATtiny87/ATtiny167 11. Timer/Counter1 Prescaler 11.1 Overview Most bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number. 11.1.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a clock source.
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1 pin to the counter is updated. Enabling and disabling of the clock input must be done when T1 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling.
ATtiny87/ATtiny167 11.2 11.2.1 Timer/Counter1 Prescalers Register Description General Timer/Counter Control Register – GTCCR Bit 7 6 5 4 3 2 1 0 TSM – – – – – PSR0 PSR1 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode.
12. 16-bit Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: 12.1 Features • • • • • • • • • • • • 12.2 True 16-bit Design (i.e.
ATtiny87/ATtiny167 Figure 12-1. 16-bit Timer/Counter1 Block Diagram(1) Count TOVn (Int.Req.) Clear Direction Control Logic clk Tn Clock Select Edge Detector TOP ( From Prescaler ) Timer/Counter TCNTn = =0 OCFnA (Int.Req.) Waveform Generation = OCRnA OCnAU OCnAV Fixed TOP Values DATABUS Tn BOTTOM OCnAW OCFnB (Int.Req.) Waveform Generation = OCRnB OCnAX OCnBU OCnBV OCnBW OCnBX ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: 12.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkTn). The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time.
ATtiny87/ATtiny167 12.3.1 Code Examples The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access. Assembly Code Examples(1) ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF sts TCNT1H,r17 sts TCNT1L,r16 ; Read TCNT1 into r17:r16 lds r16,TCNT1L lds r17,TCNT1H ...
The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATtiny87/ATtiny167 The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
12.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 12-2 shows a block diagram of the counter and its surroundings. Figure 12-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
ATtiny87/ATtiny167 The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 12.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit.
Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 112. 12.6.1 Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICP1). Only Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the Input Capture unit.
ATtiny87/ATtiny167 12.7 Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1A/B). If TCNT equals OCR1A/B the comparator signals a match. A match will set the Output Compare Flag (OCF1A/B) at the next timer clock cycle. If enabled (OCIE1A/B = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF1A/B flag is automatically cleared when the interrupt is executed.
The OCR1A/B Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1A/B Buffer Register, and if double buffering is disabled the CPU will access the OCR1A/B directly. The content of the OCR1A/B (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1A/B is not read via the high byte temporary register (TEMP).
ATtiny87/ATtiny167 Figure 12-6 shows a simplified schematic of the logic affected by the COM1A/B1:0 and OCnxi bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM1A/B1:0 and OCnxi bits are shown. When referring to the OC1A/B state, the reference is for the internal OC1A/B Register, not the OC1A/Bi pin. If a system reset occur, the OC1A/B Register is reset to “0”.
Figure 12-6. Compare Match Output Logic OCnxi COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnxi Pin Q PORT D Q clk I/O DDR 12.8.1 Compare Output Function The general I/O port function is overridden by the Output Compare (OC1A/B) from the Waveform Generator if either of the COM1A/B1:0 bits are set and if OCnxi respective bit is set in TCCR1D register.
ATtiny87/ATtiny167 or toggle at a compare match (See ”Compare Match Output Unit” on page 120.). The OCnxi bits over control the setting of the COM1A/B1:0 bits as shown in Figure 12-6 on page 122. For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 130. 12.9.1 Normal Mode The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed.
An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature.
ATtiny87/ATtiny167 In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 12-8. The figure shows fast PWM mode when OCR1A or ICR1 is used to define TOP.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1A/B pins.
ATtiny87/ATtiny167 In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 12-9.
It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the two modes of operation. In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC1A/B pins.
ATtiny87/ATtiny167 In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 12-10.
In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1A/B pins. Setting the COM1A/B1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1A/B1:0 to three (See Table on page 133). The actual OC1A/B value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1A/B) and OC1A/Bi is set.
ATtiny87/ATtiny167 Figure 12-12. Timer/Counter Timing Diagram, Setting of OCF1A/B, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 12-13 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1A/B Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
Figure 12-14. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM TOP - 1 TOP TOP - 1 BOTTOM + 1 TOP - 2 TOVn(FPWM) and ICF n (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) New OCRnx Value 12.11 16-bit Timer/Counter Register Description 12.11.
ATtiny87/ATtiny167 Table 12-2 shows the COM1A/B1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 12-2. Compare Output Mode, Fast PWM (1) OC1Ai OC1Bi COM1A1 COM1B1 COM1A0 COM1B0 0 x x 1 0 0 Description Normal port operation, OC1A/OC1B disconnected. 1 0 1 WGM13=0: Normal port operation, OC1A/OC1B disconnected. WGM13=1: Toggle OC1A on Compare Match, OC1B reserved.
• Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 12-4. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 122.).
ATtiny87/ATtiny167 12.11.2 Timer/Counter1 Control Register B – TCCR1B Bit 7 6 5 4 3 2 1 0 ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1B • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP1) is filtered.
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 12.11.
ATtiny87/ATtiny167 12.11.5 Timer/Counter1 – TCNT1H and TCNT1L Bit 7 6 5 4 3 2 1 0 TCNT1[15:8] TCNT1H TCNT1[7:0] TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter.
12.11.8 Input Capture Register – ICR1H and ICR1L Bit 7 6 5 4 3 2 1 0 ICR1[15:8] ICR1H ICR1[7:0] ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size.
ATtiny87/ATtiny167 12.11.10 Timer/Counter1 Interrupt Flag Register – TIFR1 Bit 7 6 5 4 3 2 1 0 – – ICF1 – – OCF1B OCF1A TOV1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR1 • Bit 7..6 – Reserved Bits These bits are reserved for future use. • Bit 5 – ICF1: Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin.
13. SPI - Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATtiny87/167 and peripheral devices or between several AVR devices. The ATtiny87/167 SPI includes the following features: 13.
ATtiny87/ATtiny167 The interconnection between Master and Slave CPUs with SPI is shown in Figure 13-2. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 13-1. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 72. Table 13-1. Pin SPI Pin Overrides(1) Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1.
ATtiny87/ATtiny167 Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
ATtiny87/ATtiny167 13.2 13.2.1 SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
• Bit 5 – DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. • Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set.
ATtiny87/ATtiny167 13.2.4 SPI Status Register – SPSR Bit 7 6 5 4 3 2 1 0 SPIF WCOL – – – – – SPI2X Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 SPSR • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF flag.
13.3 Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 13-3 and Figure 13-4. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 13-2 and Table 13-3, as done below: Table 13-5.
ATtiny87/ATtiny167 14. USI – Universal Serial Interface 14.1 Features • • • • • • 14.2 Two-wire Synchronous Data Transfer (Master or Slave) Three-wire Synchronous Data Transfer (Master or Slave) Data Received Interrupt Wakeup from Idle Mode In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode Two-wire Start Condition Detector with Interrupt Capability Overview The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication.
A transparent latch is inserted between the USI Data Register Output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration. The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the USI Data Register and the counter are clocked simultaneously by the same clock source.
ATtiny87/ATtiny167 The clock is generated by the Master device software by toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR. Figure 14-3. Three-wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The Three-wire mode timing is shown in Figure 14-3 At the top of the figure is a USCK cycle reference.
sts USICR,r16 lds r16, USISR sbrs r16, USIOIF rjmp SPITransfer_loop lds r16,USIDR ret The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRA or DDRB Register. The value stored in register r16 prior to the function is called is transferred to the Slave device, and when the transfer is completed the data received from the Slave is stored back into the r16 Register.
ATtiny87/ATtiny167 14.3.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ldi r16,(1<
Figure 14-4. Two-wire Mode Operation, Simplified Diagram VCC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL HOLD SCL Two-wire Clock Control Unit SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL PORTxn MASTER Figure 14-4 shows two USI units operating in Two-wire mode, one as Master and one as Slave. It is only the physical layer that is shown since the system operation is highly dependent of the communication scheme used.
ATtiny87/ATtiny167 Referring to the timing diagram (Figure 14-5), a bus transfer involves the following steps: 1. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift Register, or by setting the corresponding bit in the PORT Register to zero. Note that the USI Data Register bit must be set to one for the output to be enabled. The slave device’s start detector logic (Figure 14-6.
14.4 Alternative USI Usage When the USI unit is not used for serial communication, it can be set up to do alternative tasks due to its flexible design. 14.4.1 Half-duplex Asynchronous Data Transfer By utilizing the USI Data Register in Three-wire mode, it is possible to implement a more compact and higher performance UART than by software only. 14.4.2 4-bit Counter The 4-bit counter can be used as a stand-alone counter with overflow interrupt.
ATtiny87/ATtiny167 Note that the corresponding Data Direction Register to the pin must be set to one for enabling data output from the USI Data Register. 14.5.2 USIBR – USI Buffer Register Bit 7 6 5 4 3 2 1 0 USIB7 USIB6 USIB5 USIB4 USIB3 USIB2 USIB1 USIB0 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 USIBR • Bits 7:0 – USID7..
• Bits 3:0 – USICNT3..0: Counter Value These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or written by the CPU. The 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe bits. The clock source depends of the setting of the USICS1..0 bits.
ATtiny87/ATtiny167 Table 14-1. USIWM1 0 0 1 1 Note: Relations between USIWM1..0 and the USI Operation USIWM0 Description 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal. 1 Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORT Register in this mode. However, the corresponding DDR bit still controls the data direction. When the port pin is set as input the pins pull-up is controlled by the PORT bit.
Table 14-2. Relations between the USICS1..
ATtiny87/ATtiny167 14.5.5 USIPP – USI Pin Position Bit 7 6 5 4 3 2 1 0 - - - - - - - USIPOS Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 USIPP • Bits 7:1 – Res: Reserved Bits These bits are reserved bits in the ATtiny87/167 and always reads as zero. • Bit 0 – USIPOS: USI Pin Position Setting or clearing this bit changes the USI pin position. Table 14-3.
15. LIN / UART - Local Interconnect Network Controller or UART The LIN (Local Interconnect Network) is a serial communications protocol which efficiently supports the control of mechatronics nodes in distributed automotive applications.
ATtiny87/ATtiny167 15.3 15.3.1 LIN Protocol Master and Slave A LIN cluster consists of one master task and several slave tasks. A master node contains the master task as well as a slave task. All other nodes contain a slave task only. Figure 15-1. LIN cluster with one master node and “n” slave nodes master node master task slave node 1 slave node n slave task slave task slave task LIN bus The master task decides when and which frame shall be transferred on the bus.
15.3.3 Data Transport Two types of data may be transported in a frame; signals or diagnostic messages. • Signals Signals are scalar values or byte arrays that are packed into the data field of a frame. A signal is always present at the same position in the data field for all frames with the same identifier. • Diagnostic messages Diagnostic messages are transported in frames with two reserved identifiers.
ATtiny87/ATtiny167 15.4.1 LIN Overview The LIN/UART controller is designed to match as closely as possible to the LIN software application structure. The LIN software application is developed as independent tasks, several slave tasks and one master task (c.f. Section 15.3.4 on page 164). The ATtiny87/167 conforms to this perspective. The only link between the master task and the slave task will be at the cross-over point where the interrupt routine is called once a new identifier is available.
15.4.3 LIN/UART Controller Structure Figure 15-4. LIN/UART Controller Block Diagram CLK IO Finite State Machine Prescaler Sample /bit RxD FSM BAUD_RATE Get Byte RX Put Byte TX Frame Time-out TxD Synchronization Monitoring Data FIFO 15.4.4 BUFFER LIN/UART Command Overview Figure 15-5.
ATtiny87/ATtiny167 Table 15-1. LIN/UART Command List LENA LCMD[2] LCMD[1] LCMD[0] Command 0 x x x Disable peripheral 0 Rx Header - LIN Abort LIN Withdrawal 1 Tx Header LCMD[2..0]=000 after Tx 0 Rx Response LCMD[2..0]=000 after Rx 1 Tx Response LCMD[2..0]=000 after Tx 0 0 Byte transfer 1 0 Rx Byte 0 1 Tx Byte 1 1 Full duplex 0 0 1 1 1 15.4.
15.4.6.2 Tx Header Function In accordance with the LIN protocol, only the master task must enable this function. The header is sent in the appropriate timed slots at the programmed baud rate (c.f. LINBRR & LINBTR registers). The controller is responsible for: • The transmission of the BREAK field - 13 dominant bits, • The transmission of the SYNCH field - character 0x55, • The transmission of the PROTECTED IDENTIFIER field. It is the full content of the LINIDR register (automatic check bits included).
ATtiny87/ATtiny167 15.4.6.4 Handling Data of LIN response A FIFO data buffer is used for data of the LIN response. After setting all parameters in the LINSEL register, repeated accesses to the LINDAT register perform data read or data write (c.f. “Data Management” on page 179). Note that LRXDL[3..0] and LTXDL[3..0] are not linked to the data access. 15.4.7 UART Commands Setting the LCMD[2] bit in LINENR register enables UART commands.
15.5 15.5.1 LIN / UART Description Reset The AVR core reset logic signal also resets the LIN/UART controller. Another form of reset exists, a software reset controlled by LSWRES bit in LINCR register. This self-reset bit performs a partial reset as shown in Table 15-2. Table 15-2. 15.5.2 Reset of LIN/UART Registers Register Name Reset Value LSWRES Value LIN Control Reg. LINCR 0000 0000 b 0000 0000 b LIN Status & Interrupt Reg. LINSIR 0000 0000 b 0000 0000 b LIN Enable Interrupt Reg.
ATtiny87/ATtiny167 15.5.4 Configuration Depending on the mode (LIN or UART), LCONF[1..0] bits of the LINCR register set the controller in the following configuration (Table 15-3): Table 15-3. Mode LIN UART Configuration Table versus Mode LCONF[1..
When the busy signal is set, some registers are locked, user writing is not allowed: • “LIN Control Register” - LINCR - except LCMD[2..0], LENA & LSWRES, • “LIN Baud Rate Registers” - LINBRRL & LINBRRH, • “LIN Data Length Register” - LINDLR, • “LIN Identifier Register” - LINIDR, • “LIN Data Register” - LINDAT. If the busy signal is set, the only available commands are: • LCMD[1..
ATtiny87/ATtiny167 The re-synchronization implemented in the controller tolerates a clock deviation of ± 20% and adjusts the baud rate in a ± 2% range. The new LBT[5..0] value will be used up to the end of the response. Then, the LBT[5..0] will be reset to 32 for the next header. The LINBTR register can be used to (software) re-calibrate the clock oscillator. The re-synchronization is not performed if the LIN node is enabled as a master. 15.5.6.3 Handling LBT[5..
15.5.7.2 Data Length in LIN 1.3 • LRXDL and LTXDL fields are both hardware updated before setting LIDOK by decoding the data length code contained in the received PROTECTED IDENTIFIER (LRXDL = LTXDL). • Via the above mechanism, a length of 0 or >8 is not possible. 15.5.7.3 Data Length in Rx Response Figure 15-9. LIN2.1 - Rx Response - No error LIDOK LIN bus LRXDL (*) 4 LTXDL (*) ? LRXOK 1st Byte 2 nd Byte 3 rd Byte 4 th Byte DATA-0 DATA-1 DATA-2 DATA-3 CHECKSUM 1 2 3 4 0 LBUSY LCMD2..
ATtiny87/ATtiny167 • If an error occurs, Tx stops, the corresponding error flag is set and LRXDL will give the number of transmitted bytes without error, • If no error occurs, LTXOK is set after the transmission of the CHECKSUM, LTXDL will be unchanged (and LRXDL = LTXDL). 15.5.7.5 Data Length after Error Figure 15-11. Tx Response - Error LIN bus 1st Byte 2 nd Byte DATA-0 DATA-1 3 rd Byte LERR DATA-2 ERROR LRXDL 4 LTXDL 4 0 1 2 LBUSY LCMD2..0=000b LCMD=Tx Response Note: 15.5.7.
15.5.9 xxERR Flags LERR bit of the LINSIR register is an logical ‘OR’ of all the bits of LINERR register (see Section 15.5.13 “Interrupts” on page 178). There are eight flags: • LBERR = LIN Bit ERRor. A unit that is sending a bit on the bus also monitors the bus. A LIN bit error will be flagged when the bit value that is monitored is different from the bit value that is sent. After detection of a LIN bit error the transmission is aborted. • LCERR = LIN Checksum ERRor.
ATtiny87/ATtiny167 15.5.10 Frame Time Out According to the LIN protocol, a frame time-out error is flagged if: T Frame > T Frame_Maximum. This feature is implemented in the LIN/UART controller. Figure 15-12.
⎛ ⎛n ⎞ ⎛⎛ n ⎞ ⎞⎞ ⎜ ⎜ ⎟ CHECKSUM = 255 – unsigned char ∑DATA n + unsigned char ⎜ ⎜ ∑DATA n⎟ » 8⎟ ⎟ ⎜ ⎜ ⎟ ⎜⎜ ⎟ ⎟⎟ ⎝ ⎝0 ⎠ ⎝⎝ 0 ⎠ ⎠⎠ Frame identifiers 60 (0x3C) to 61 (0x3D) shall always use classic checksum. 15.5.13 Interrupts As shown in Figure 15-13 on page 178, the four communication flags of the LINSIR register are combined to drive two interrupts. Each of these flags have their respective enable interrupt bit in LINENIR register. (see Section 15.5.8 “xxOK Flags” on page 175 and Section 15.5.
ATtiny87/ATtiny167 The LIN protocol says that a message with an identifier from 60 (0x3C) up to 63 (0x3F) uses a classic checksum (sum over the data bytes only). Software will be responsible for switching correctly the LIN13 bit to provide/check this expected checksum (the insertion of the ID field in the computation of the CRC is set - or not - just after entering the Rx or Tx Response command). 15.5.15 15.5.15.
15.6 LIN / UART Register Description Table 15-5.
ATtiny87/ATtiny167 15.6.1 LIN Control Register - LINCR Bit 7 6 5 4 3 2 1 0 LSWRES LIN13 LCONF1 LCONF0 LENA LCMD2 LCMD1 LCMD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 LINCR • Bit 7 - LSWRES: Software Reset – 0 = No action, – 1 = Software reset (this bit is self-reset at the end of the reset procedure). • Bit 6 - LIN13: LIN 1.3 mode – 0 = LIN 2.1 (default), – 1 = LIN 1.3. • Bit 5:4 - LCONF[1:0]: Configuration a.
15.6.2 LIN Status and Interrupt Register - LINSIR Bit 7 6 5 4 3 2 1 0 LIDST2 LIDST1 LIDST0 LBUSY LERR LIDOK LTXOK LRXOK Read/Write R R R R R/Wone R/Wone R/Wone R/Wone Initial Value 0 0 0 0 0 0 0 0 LINSIR • Bits 7:5 - LIDST[2:0]: Identifier Status – 0xx = no specific identifier, – 100 = Identifier 60 (0x3C), – 101 = Identifier 61 (0x3D), – 110 = Identifier 62 (0x3E), – 111 = Identifier 63 (0x3F).
ATtiny87/ATtiny167 • Bit 0 - LRXOK: Receive Performed Interrupt This bit generates an interrupt if its respective enable bit - LENRXOK - is set in LINENIR. – 0 = No Rx – 1 = Rx Response complete. The user clears this bit by writing 1, in order to reset this interrupt. In UART mode, this bit is also cleared by reading LINDAT. 15.6.
• Bit 6 - LTOERR: Frame_Time_Out Error Flag – 0 = No error, – 1 = Frame_Time_Out error. This bit is cleared when LERR bit in LINSIR is cleared. • Bit 5 - LOVERR: Overrun Error Flag – 0 = No error, – 1 = Overrun error. This bit is cleared when LERR bit in LINSIR is cleared. • Bit 4 - LFERR: Framing Error Flag – 0 = No error, – 1 = Framing error. This bit is cleared when LERR bit in LINSIR is cleared. • Bit 3 - LSERR: Synchronization Error Flag – 0 = No error, – 1 = Synchronization error.
ATtiny87/ATtiny167 • Bits 5:0 - LBT[5:0]: LIN Bit Timing Gives the number of samples of a bit. sample-time = (1 / fclki/o ) x (LDIV[11..0] + 1) Default value: LBT[6:0]=32 — Min. value: LBT[6:0]=8 — Max. value: LBT[6:0]=63 15.6.
15.6.8 LIN Identifier Register - LINIDR Bit 7 6 5 4 3 2 1 0 LP1 LP0 LID5 / LDL1 LID4 / LDL0 LID3 LID2 LID1 LID0 Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 LINIDR • Bits 7:6 - LP[1:0]: Parity In LIN mode: LP0 = LID4 ^ LID2 ^ LID1 ^ LID0 LP1 = ! ( LID1 ^ LID3 ^ LID4 ^ LID5 ) In UART mode this field is unused. • Bits 5:4 - LDL[1:0]: LIN 1.3 Data Length In LIN 1.
ATtiny87/ATtiny167 • Bit 3 - LAINC: Auto Increment of Data Buffer Index In LIN mode: – 0 = Auto incrementation of FIFO data buffer index (default), – 1 = No auto incrementation. In UART mode this field is unused. • Bits 2:0 - LINDX 2:0: FIFO LIN Data Buffer Index In LIN mode: location (index) of the LIN response data byte into the FIFO data buffer. The FIFO data buffer is accessed through LINDAT. In UART mode this field is unused. 15.6.
16. ISRC - Current Source 16.1 Features • 100µA Constant current source • ±10% Absolute Accuracy The ATtiny87/167 features a 100µA ±10% Current Source. Up on request, the current is flowing through an external resistor. The voltage can be measured on the dedicated pin shared with the ADC. Using a resistor in serie with a ≤ 0.5% tolerance is recommended. To protect the device against big values, the ADC must be configured with AVcc as internal reference to perform the first measurement.
ATtiny87/ATtiny167 In automotive applications, distributed voltages are very disturbed. The internal Current Source solution of ATtiny87/167 immunizes the address detection the against any kind of voltage variations. Table 16-1. Example of Resistor Values(±5%) for a 8-address System (AVcc = 5V(1)) Minimum Reading with a 2.56V ref Typical Reading with a 2.56V ref Physical Address Resistor Value Rload (Ohm) Typical Measured Voltage (V) 0 1 000 0.1 40 1 2 200 0.22 88 2 3 300 0.
16.2.2 Current Source for Low Cost Transducer An external transducer based on a variable resistor can be connected to the Current Source. This can be, for instance: • A thermistor, or temperature-sensitive resistor, used as a temperature sensor, • A CdS photoconductive cell, or luminosity-sensitive resistor, used as a luminosity sensor, • ... Using the Current Source with this type of transducer eliminates the need for additional parts otherwise required in resistor network or Wheatstone bridge. 16.2.
ATtiny87/ATtiny167 17. ADC – Analog to Digital Converter 17.1 Features • • • • • • • • • • • • • • • • • • 17.2 10-bit Resolution 1.
Figure 17-1. Analog to Digital Converter Block Schematic Internal 2.56 / 1.1V Reference ADC Data Register (ADCH / ADCL) Trigger Select Interrupt Flags ADC[9..0] ADSC ADATE ADTS[2..0] ADIF ADEN BIN ADLAR MUX[4..0] REFS0 REFS1 ADPS[2..0] ADC Control & Status Register A & B (ADCSRA/ADCSRB) ADC Multiplexer Select (ADMUX) AREFEN XREFEN Analog Misc. (AMISCR) ADC Conversion Complete IRQ ADIF ADIE 8-Bit Data Bus Prescaler Start Mux.
ATtiny87/ATtiny167 17.3 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents AGND and the maximum value represents the voltage on AVcc, the voltage refrence on AREF pin or an internal 1.1V / 2.56V voltage reference. The voltage reference for the ADC may be selected by writing to the REFS[1..0] bits in ADMUX and AREFEN bit in AMISCR. The AVcc supply, the AREF pin or an internal 1.1V / 2.
17.4 Starting a Conversion A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. Alternatively, a conversion can be triggered automatically by various sources.
ATtiny87/ATtiny167 17.5 Prescaling and Conversion Timing Figure 17-3. ADC Prescaler ADEN Reset Start 7-bit ADC Prescaler CK/128 CK/64 CK/32 CK/8 CK/16 CK/4 CK/2 CLK IO ADPS0 ADPS1 ADPS2 By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.
Figure 17-4. ADC Timing Diagram, First Conversion (Single Conversion Mode) Next Conversion First Conversion ycle Number 1 2 13 12 14 15 16 17 18 19 20 21 22 24 23 25 1 2 3 DC Clock DEN DSC DIF Sign and MSB of Result DCH LSB of Result DCL MUX and REFS Update MUX and REFS Update Conversion Complete Sample & Hold Figure 17-5.
ATtiny87/ATtiny167 Figure 17-7. ADC Timing Diagram, Free Running Conversion One Conversion ycle Number 11 12 Next Conversion 13 1 2 3 4 DC Clock DSC DIF DCH Sign and MSB of Result DCL LSB of Result Sample & Hold Conversion Complete Table 17-1. MUX and REFS Update ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 cycles 25 cycles Normal conversions 1.5 cycles 13 cycles 2 cycles 13.
17.6.1 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection.
ATtiny87/ATtiny167 The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or less. If such a source is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor.
Figure 17-9. Offset Error Output Code Ideal ADC Actual ADC Offset Error VREF Input Voltage • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 17-10.
ATtiny87/ATtiny167 Figure 17-11. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF Input Voltage • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 17-12.
17.8 ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). The form of the conversion result depends on the type of the conversion as there are three types of conversions: single ended conversion, unipolar differential conversion and bipolar differential conversion. 17.8.
ATtiny87/ATtiny167 However, if the signal is not bipolar by nature (9 bits + sign as the 10th bit), this scheme loses one bit of the converter dynamic range. Then, if the user wants to perform the conversion with the maximum dynamic range, the user can perform a quick polarity check of the result and use the unipolar differential conversion with selectable differential input pair. When the polarity check is performed, it is sufficient to read the MSB of the result (ADC9 in ADCH register).
The following code example allows to read Signature Row data: .equ TS_GAIN = 0x0007 .
ATtiny87/ATtiny167 17.11 Register Description 17.11.1 ADMUX – ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADMUX • Bit 7:6 – REFS1:REFS0: Voltage Reference Selection Bits These bits and AREFEN bit from the Analog Miscellaneous Control Register (AMISCR) select the voltage reference for the ADC, as shown in Table 17-4.
Table 17-5. Input Channel Selections MUX[4..0] Single Ended Input 0 0000 ADC0 (PA0) 0 0001 ADC1 (PA1) 0 0010 ADC2 (PA2) 0 0011 ADC3 / ISRC (PA3) 0 0100 ADC4 (PA4) 0 0101 ADC5 (PA5) 0 0110 ADC6 (PA6) 0 0111 ADC7 / AREF (PA7) 0 1000 ADC8 (PB5) 0 1001 ADC9 (PB6) 0 1010 ADC10 (PB7) 0 1011 Temperature Sensor 0 1100 Bandgap Reference (1.
ATtiny87/ATtiny167 17.11.2 ADCSRA – ADC Control and Status Register A Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
Table 17-6. 17.11.3 17.11.3.1 ADPS2 ADPS1 ADPS0 Division Factor 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 ADCL and ADCH – The ADC Data Register ADLAR = 0 Bit Read/Write Initial Value 17.11.3.
ATtiny87/ATtiny167 17.11.4 ADCSRB – ADC Control and Status Register B Bit 7 6 5 4 3 2 1 0 BIN ACME ACIR1 ACIR0 – ADTS2 ADTS1 ADTS0 Read/Write R/W R/W R/W R/W R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB • Bit 7– BIN: Bipolar Input Mode The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected by writing the BIN bit in the ADCSRB register.
• Bits 7:0 – ADC7D:ADC0D: ADC7:0 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 17.11.
ATtiny87/ATtiny167 18. AnaComp - Analog Comparator The Analog Comparator compares the input values on the positive pin (AIN1) and negative pin (AIN0). When the voltage on the positive pin is higher than the voltage on the negative pin, the Analog Comparator output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle.
• Bits 5, 4 – ACIR1, ACIR0: Analog Comparator Internal Voltage Reference Select When ACIRS bit is set in ADCSRA register, these bits select a voltage reference for the negative input to the Analog Comparator, see Table 18-3 on page 214. 18.1.
ATtiny87/ATtiny167 Table 18-1. ACIS1 ACIS0 0 0 Comparator Interrupt on Output Toggle. 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Output Edge. Note: 18.1.3 ACIS1 / ACIS0 Settings Interrupt Mode When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed.
Table 18-2. 18.2.2 ACME ADEN MUX[4..0] 0 x x xxxx b AIN1 x 1 x xxxx b AIN1 1 0 0 0000 b ADC0 1 0 0 0001 b ADC1 1 0 0 0010 b ADC2 1 0 0 0011 b ADC3 / ISRC 1 0 0 0100 b ADC4 1 0 0 0101 b ADC5 1 0 0 0110 b ADC6 1 0 0 0111 b ADC7 1 0 0 1000 b ADC8 1 0 0 1001 b ADC9 1 0 0 1010 b ADC10 1 0 Other Analog Comparator Positive Input - Comment ADC Switched On ADC Switched Off. This doesn’t make sense - Don’t use.
ATtiny87/ATtiny167 19. DebugWIRE On-chip Debug System 19.1 Features • • • • • • • • • • 19.
• Pull-up resistors on the dW/(RESET) line must not be smaller than 10kΩ. The pull-up resistor is not required for debugWIRE functionality. • Connecting the RESET pin directly to Vcc will not work. • Capacitors connected to the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. 19.4 Software Break Points DebugWIRE supports Program memory break points by the AVR BREAK instruction.
ATtiny87/ATtiny167 20. Flash Programming The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface (i.e. LIN, USART, ...) and associated protocol to read code and write (program) that code into the Program memory. The Program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
20.1.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101 b” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. • The CPU is halted during the Page Write operation. 20.2 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands.
ATtiny87/ATtiny167 20.2.1 Store Program Memory Control and Status Register – SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations. Bit 7 6 5 4 3 2 1 0 – RWWSB SIGRD CTPB RFLB PGWRT PGERS SPMEN Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPMCSR • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny87/167 and will always read as zero.
• Bit 0 – SPMEN: Self Programming Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either SIGRD, CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored.
ATtiny87/ATtiny167 Similarly, when reading the Extended Fuse byte (EFB), load 0x0002 in the Z-pointer. When an LPM instruction is executed within three cycles after the RFLB and SPMEN bits are set in the SPMCSR, the value of the Extended Fuse byte will be loaded in the destination register as shown below. See Table 21-3 on page 226 for detailed description and mapping of the Extended Fuse byte.
20.2.5 Preventing Flash Corruption During periods of low Vcc, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. • First, a regular write sequence to the Flash requires a minimum voltage to operate correctly.
ATtiny87/ATtiny167 20.2.7 Simple Assembly Code Example for a Boot Loader Note that the RWWSB bit will always be read as zero in ATtiny87/167. Nevertheless, it is recommended to check this bit as shown in the code example, to ensure compatibility with devices supporting Read-While-Write.
ld cpse rjmp sbiw brne r1, Y+ r0, r1 Error loophi:looplo, 1 Rdloop ; use subi for PAGESIZEB<=256 ; To ensure compatibility with devices supporting Read-While-Write ; Return to RWW section ; Verify that RWW section is safe to read Return: in temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; Clear temporary page buffer ldi spmcsrval, (1<
ATtiny87/ATtiny167 21. Memory Programming 21.1 Program and Data Memory Lock Bits The ATtiny87/167 provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 21-2. The Lock bits can only be erased to “1” with the Chip Erase command. The ATtiny87/167 has no separate Boot Loader section. Table 21-1.
Note that the fuses are read as logical zero, “0”, if they are programmed. Table 21-3. Extended Fuse Byte Fuse Extended Byte Bit No Description Default Value – 7 – 1 (unprogrammed) – 6 – 1 (unprogrammed) – 5 – 1 (unprogrammed) – 4 – 1 (unprogrammed) – 3 – 1 (unprogrammed) – 2 – 1 (unprogrammed) – 1 – 1 (unprogrammed) SELFPRGEN 0 Self Programming Enable 1 (unprogrammed) Table 21-4.
ATtiny87/ATtiny167 Table 21-5. Fuse Low Byte Fuse Low Byte Bit No Description Default Value CKDIV8(4) 7 Divide clock by 8 0 (programmed) CKOUT(3) 6 Clock output 1 (unprogrammed) SUT1 5 Select start-up time 1 (unprogrammed)(1) SUT0 4 Select start-up time 0 (programmed)(1) CKSEL3 3 Select Clock source 0 (programmed)(2) CKSEL2 2 Select Clock source 0 (programmed)(2) CKSEL1 1 Select Clock source 1 (unprogrammed)(2) CKSEL0 0 Select Clock source 0 (programmed)(2) Notes: 1.
21.4 Calibration Byte The ATtiny87/167 has a byte calibration value for the internal RC Oscillator. This byte resides in the high byte of address 0x000 in the signature address space. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator. 21.5 Page Size Table 21-7. Device Flash Size Page Size PCWORD No.
ATtiny87/ATtiny167 Figure 21-1. Parallel programming WR PB0 XA0 PB1 XA1 / BS2 PB2 PAGEL / BS1 PB3 +4.5 - +5.5V Vcc +4.5 - +5.5V AVcc XTAL1 / PB4 OE PB5 RDY / BSY PB6 +12 V PA7 - PA0 DATA RESET / PB7 GND Note: Vcc - 0.3V < AVcc < Vcc + 0.3V, however, AVcc should always be within 4.5 - 5.5V Table 21-9. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O WR PB0 I Write Pulse (Active low).
Table 21-10. Pin Values Used to Enter Programming Mode Pin Symbol Value PAGEL / BS1 Prog_enable[3] 0 XA1 / BS2 Prog_enable[2] 0 XA0 Prog_enable[1] 0 WR Prog_enable[0] 0 Table 21-11. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1). 1 0 Load Command 1 1 No Action, Idle Table 21-12.
ATtiny87/ATtiny167 21.7 21.7.1 Parallel Programming Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5 - 5.5V between Vcc and GND. 2. Set RESET to “0” and toggle XTAL1 at least six times. 3. Set the Prog_enable pins listed in Table 21-10 on page 230 to “0000 b” and wait at least 100 ns. 4. Apply 11.5 - 12.5V to RESET.
21.7.4 Programming the Flash The Flash is organized in pages, see Table 21-7 on page 228. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “1,0”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000 b”. This is the command for Write Flash. 4.
ATtiny87/ATtiny167 G. Load Address High byte 1. Set XA1, XA0 to “0,0”. This enables address loading. 2. Set BS1 to “1”. This selects high address. 3. Set DATA = Address high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address high byte. H. Program Page 1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 2. Wait until RDY/BSY goes high (See Figure 21-3 for signal waveforms). I.
Figure 21-3. Programming the Flash Waveforms (1) F DATA A B 0x10 ADDR. LOW C DATA LOW D DATA HIGH E XX B ADDR. LOW C DATA LOW D DATA HIGH E XX G ADDR. HIGH H XX XA1 / BS2 XA0 PAGEL / BS1 XTAL1 WR RDY/BSY RESET +12V OE Note: 21.7.5 1. “XX” is don’t care. The letters refer to the programming description above. Programming the EEPROM The EEPROM is organized in pages, see Table 21-8 on page 228. When programming the EEPROM, the program data is latched into a page buffer.
ATtiny87/ATtiny167 Figure 21-4. Programming the EEPROM Waveforms K A DATA 0x11 G ADDR. HIGH B ADDR. LOW C E B DATA XX ADDR. LOW C DATA E L XX XA1 / BS2 XA0 PAGEL / BS1 XTAL1 WR RDY/BSY RESET +12V OE 21.7.6 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 232 for details on Command and Address loading): 1. A: Load Command “0000 0010 b”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4.
21.7.9 Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (refer to “Programming the Flash” on page 232 for details on Command and Data loading): 1. A: Load Command “0100 0000 b”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS1 to “1” and BS2 to “0”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to “0”. This selects low data byte. 21.7.
ATtiny87/ATtiny167 21.7.12 Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash” on page 232 for details on Command loading): 1. A: Load Command “0000 0100 b”. 2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed). 3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be read at DATA (“0” means programmed). 4.
21.7.15 Reading the Temperature Sensor Parameter Bytes The algorithm for reading the Temperature Sensor parameter bytes is as follows (refer to “Programming the Flash” on page 232 for details on Command and Address loading): 1. A: Load Command “0000 1000 b”. 2. B: Load Address Low Byte, 0x0003 or 0x0005. 3. Set OE to “0”, and BS1 to “1”. The Temperature Sensor parameter byte can now be read at DATA. 4. Set OE to “1”. 21.
ATtiny87/ATtiny167 Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz 21.8.1 Serial Programming Algorithm When writing serial data to the ATtiny87/167, data is clocked on the rising edge of SCK.
7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Turn Vcc power off. Table 21-14. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol 21.8.2 Minimum Wait Delay t WD_FLASH 4.5 ms t WD_EEPROM 4.0 ms t WD_ERASE 4.0 ms t WD_FUSE 4.5 ms Serial Programming Instruction set Table 21-15 on page 240 and Figure 21-8 on page 242 describes the Instruction set Table 21-15.
ATtiny87/ATtiny167 Table 21-15. Serial Programming Instruction Set (Continued) Instruction Format Instruction/Operation Byte 1 Byte 2 Byte 3 Byte4 Write EEPROM Memory 0xC0 0x00 00aa aaaa b data byte in Write EEPROM Memory Page (page access) 0xC2 0x00 00aa aa00 b 0x00 Write Lock bits 0xAC 0xE0 0x00 data byte in Write Fuse bits 0xAC 0xA0 0x00 data byte in Write Fuse High bits 0xAC 0xA8 0x00 data byte in Write Extended Fuse Bits 0xAC 0xA4 0x00 data byte in Notes: 1.
Figure 21-8. Serial programming Instruction Example Serial Programming Instruction Load Program Memory Page (High/Low Byte) / Load EEPROM Memory Page (Page Access) Byte 1 Byte 2 Addr. MSB Bit 15 B Byte 3 Write Program Memory Page / Write EEPROM Memory Page Byte 4 Byte 1 Byte 2 Addr. LSB Addr. MSB 0 Bit 15 B Byte 3 Byte 4 Addr. MSB 0 Page Buffer Page Offset Page 0 Page 1 Page 2 Page Number Page N-1 Program Memory / EEPROM Memory 21.9 Serial Programming Characteristics Figure 21-9.
ATtiny87/ATtiny167 22. Electrical Characteristics Note: All Characteristics contained in this data sheet are based on simulation and characterization of ATtiny87/167 AVR microcontrollers manufactured in a typical process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual Automotive silicon. 22.1 Absolute Maximum Ratings* Operating Temperature.................................– 40°C to +125°C *NOTICE: Storage Temperature ....
TA = -40°C to +125°C, Vcc = 2.7V to 5.5V (unless otherwise noted) (Continued) Typ.(1) Max. Units Vcc = 5.5V, pin low (absolute value) < 0.05 1 µA Vcc = 5.5V, pin high (absolute value) < 0.
ATtiny87/ATtiny167 22.3 Speed Grades Figure 22-1. Maximum Frequency vs. Vcc, ATtiny87/167 Frequency 16 MHz 8 MHz Safe Operating Area Voltage 2.7V 22.4 22.4.1 5.5V Clock Characteristics Calibrated Internal RC Oscillator Accuracy Table 22-1. 22.4.2 4.5V Calibration and Accuracy of Internal RC Oscillator Frequency Vcc Temperature Accuracy Factory Calibration 8.0 MHz 3V 25°C ±2% Maximum Deviation 8.0 MHz 2.7V –40°C/+125°C ±10% 5.
22.4.3 External Clock Drive Table 22-2. Symbol 1/tCLCL Vcc = 4.5 - 5.5V Min. Max. Min. Max. Units 0 8 0 16 MHz Oscillator Frequency Clock Period 125 62.5 ns tCHCX High Time 50 25 ns tCLCX Low Time 50 25 ns tCLCH Rise Time 1.6 0.5 ms tCHCL Fall Time 1.6 0.5 ms 2 2 % Change in period from one clock cycle to the next RESET Characteristics Table 22-3. Symbol External Reset Characteristics Parameter Condition Min 0.1 Vcc Typ Max Units 0.9 Vcc V 2.5 µs 1.1 1.
ATtiny87/ATtiny167 Table 22-5. BODLEVEL Fuse Coding BODLEVEL 2:0 Fuses Min. VBOT(1) Typ. VBOT Max. VBOT Units BOD Disabled 1 1 1b 1 1 0b 1.7 1.8 2.0 1 0 1b 2.5 2.7 2.9 1 0 0b 4.1 4.3 4.5 0 1 1b 0 1 0b V Reserved 0 0 1b 0 0 0b Notes: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to Vcc = VBOT during the production test.
22.7 Current Source Characteristics Table 22-8. Symbol 22.8 Current Source Characteristics Parameter Condition Min. IISRC Current Vcc = 2.7 V / 5.5 V T = -40°C / +125°C tISRC Current Source start-up time Vcc = 4.5 TA = 25°C Typ. 94 60 Max. Units 106 µA µs ADC Characteristics Table 22-9. Symbol ADC Characteristics, Single Ended Channels (-40°C/+125°C) Parameter Condition Resolution Single Ended Conversion 10 TUE Absolute accuracy Vcc = 4V, VRef = 4V, ADC clock = 200 kHz 2.0 3.
ATtiny87/ATtiny167 Table 22-10. ADC Characteristics, Differential Channels (-40°C/+125°C) Symbol TUE INL DNL Parameter Condition Resolution Differential conversion 8 Gain = 8x, BIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200 kHz 1.0 3.0 Gain = 20x, BIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200 kHz 1.5 3.5 Gain = 8x, UNIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200 kHz 2.0 4.5 Gain = 20x, UNIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200 kHz 2.0 6.
Table 22-10. ADC Characteristics, Differential Channels (-40°C/+125°C) (Continued) Symbol Parameter Offset error Condition Min Typ Max Gain = 8x or 20x, BIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200 kHz -2.0 0.5 2.0 Gain = 8x or 20x, UNIPOLAR VREF = 4V, Vcc = 5V ADC clock = 200 kHz -2.0 LSB Reference voltage VREF VDIFF AVcc Input differential voltage Analog supply voltage VIN Input voltage 0.5 2.0 2.56 AVCC - 0.5 V -VREF/Gain +VREF/Gain V Vcc - 0.3 Vcc + 0.
ATtiny87/ATtiny167 Figure 22-4. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) LOAD DATA (LOW BYTE) LOAD DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) t XLXH XTAL1 AGEL/BS1 DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1/BS2 Note: 1. The timing requirements shown in Figure 22-3 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 22-5.
Table 22-11. Parallel Programming Characteristics, VCC = 5V ± 10% Symbol Parameter Min VPP Programming Enable Voltage 11.5 IPP Programming Enable Current Max Units 12.
ATtiny87/ATtiny167 22.10 SPI Timing Characteristics See Figure 22-6 and Figure 22-7 for details. Table 22-12. SPI Timing Parameters 1 Description Mode Min. Typ. Max. SCK period Master See Table 13-4 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
Figure 22-7. SPI Interface Timing Requirements (Slave Mode) 18 SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) 254 MSB 17 ...
ATtiny87/ATtiny167 23. Decoupling Capacitors The operating frequency (i.e. system clock) of the processor determines in 95% of cases the value needed for microcontroller decoupling capacitors. The hypotheses used as first evaluation for decoupling capacitors are: • The operating frequency (fop) supplies itself the maximum peak levels of noise. The main peaks are located at fop and 2 • fop. • An SMC capacitor connected to 2 micro-vias on a PCB has the following characteristics: – 1.
24. Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled.
ATtiny87/ATtiny167 Figure 24-2. Active Supply Current vs. Frequency (≥ 1 MHz) Figure 24-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR 8MHz (No ATD influence) 9 8 ICC (mA) 7 6 150 5 125 85 4 25 3 -40 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 24-4. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR 128 KHz / ATD ON 0.2 0.18 0.16 ICC (mA) 0.14 150 0.12 125 0.1 85 0.08 25 0.06 -40 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 24.2 Idle Supply Current Figure 24-5. Idle Supply Current vs. Frequency (≥ 1 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY NO POWER REDUCTION ENABLED 10 9 8 6 ICC (mA) 7 5.5 6 5 5 4.5 4 4 3 3.6 2 3.3 1 3 2.
ATtiny87/ATtiny167 Figure 24-6. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. V CC INTERNAL RC OSCILLATOR 8MHz 3 2.5 150 ICC (mA) 2 125 1.5 85 25 1 -40 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 24-7. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR 125 KHz 0.08 0.07 0.06 150 ICC (mA) 0.05 125 0.04 85 0.03 25 -40 0.02 0.01 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
24.3 Supply Current of I/O modules The table below can be used to calculate the additional current consumption for the different I/O modules Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See Section 5.9.3 “PRR – Power Reduction Register” on page 47 for details. Table 24-1. 24.4 Additional Current Consumption for the different I/O modules (absolute values) Module Vcc = 5.0 V Freq. = 16 MHz Vcc = 5.0 V Freq. = 8 MHz Vcc = 3.0 V Freq.
ATtiny87/ATtiny167 Figure 24-9. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 40 35 30 150 ICC (uA) 25 125 20 85 15 25 -40 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 24.5 Pin Pull-up Figure 24-10. I/O Pin pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7 V 90 80 IOP (uA) 70 60 150 50 125 40 85 30 25 20 -40 10 0 -10 0 0.5 1 1.5 2 2.
Figure 24-11. I/O Pin pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5.0 V 160 140 120 150 IOP (uA) 100 125 80 85 60 25 40 -40 20 0 0 1 2 3 4 5 6 -20 V OP (V) Figure 24-12. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 2.7 V 70 60 50 IRESET (uA) 150 40 125 30 85 25 20 -40 10 0 0 0.5 1 1.5 2 2.
ATtiny87/ATtiny167 Figure 24-13. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 5.0 V 120 100 IRESET (uA) 80 150 125 60 85 25 40 -40 20 0 0 1 2 3 4 5 6 -20 V RESET (V) 24.6 Pin Driver Strength Figure 24-14. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT Vcc = 3.0 V 2 1.8 1.6 150 1.4 125 V OL (V) 1.2 85 1 25 0.8 -40 0.6 0.4 0.
Figure 24-15. I/O Pin Output Voltage vs. Sink Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT Vcc = 5.0V 1.2 1 150 V OL (V) 0.8 125 85 0.6 25 -40 0.4 0.2 0 0 5 10 15 20 25 IOL (mA) Figure 24-16. I/O Pin Output Voltage vs. Source Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT Vcc = 3.0 V 3 2.5 150 125 V OH (V) 2 85 1.5 25 -40 1 0.
ATtiny87/ATtiny167 Figure 24-17. I/O Pin Output Voltage vs. Source Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT V cc = 5.0 V 5.1 4.9 150 4.7 V OH (V) 125 4.5 85 25 4.3 -40 4.1 3.9 3.7 0 2 4 6 8 10 12 14 16 18 20 IOH (mA ) 24.7 Internal Oscillator Speed Figure 24-18. Calibrated 8.0 MHz RC Oscillator Frequency vs.
Figure 24-19. Calibrated 8.0 MHz RC Oscillator Frequency vs. OSCCAL Value 24.8 Current Consumption in Reset Figure 24-20. Reset Supply Current vs. Vcc, Frequencies 0.1 - 1.0 MHz (Excluding CurrentThrough the Reset Pull-up) RESET SUPPLY CURRENT vs. V CC EXCLUDING CURRENT THROUGH THE RESET PULLUP 0.3 6 0.25 5.5 5 ICC (mA) 0.2 4.5 4 0.15 3.6 3.3 0.1 3 0.05 2.7 2.4 0 0 0.1 0.2 0.3 0.4 0.5 Frequency (MHz) 0.6 0.7 0.8 0.9 1 2.1 2 1.8 1.
ATtiny87/ATtiny167 Figure 24-21. Reset Supply Current vs. Vcc, Frequencies ≥ 1 MHz (Excluding Current Through the Reset Pull-up) RESET SUPPLY CURRENT vs. V CC EXCLUDING CURRENT THROUGH THE RESET PULLUP 4.5 4 6 5.5 3.5 5 ICC (mA) 3 4.5 2.5 4 2 3.6 1.5 3.3 3 1 2.7 0.5 2.4 0 2.1 0 2 4 6 8 10 Frequency (MHz) 12 14 16 18 20 2 1.8 1.
25.
ATtiny87/ATtiny167 Address Name (0xBE) Reserved (0xBD) Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xBC) USIPP USIPOS page 161 (0xBB) USIBR USIB7 USIB6 USIB5 USIB4 USIB3 USIB2 USIB1 USIB0 page 157 (0xBA) USIDR USID7 USID6 USID5 USID4 USID3 USID2 USID1 USID0 page 156 (0xB9) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 page 157 (0xB8) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC page 158 (0xB7)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 page 205 (0x7B) ADCSRB BIN ACME ACIR1 ACIR0 – ADTS2 ADTS1 ADTS0 page 209, page 211 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 207 (0x79) ADCH - / ADC9 - / ADC8 - / ADC7 - / ADC6 - / ADC5 - / ADC4 ADC9 / ADC3 ADC8 / ADC2 page 208 (0x78) ADCL ADC7 / ADC1 ADC6 / ADC0 ADC5 / - ADC4 / - ADC3 / - ADC2 / - ADC1 /
ATtiny87/ATtiny167 Address Name 0x1A (0x3A) Reserved 0x19 (0x39) Reserved 0x18 (0x38) Reserved 0x17 (0x37) Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x16 (0x36) TIFR1 – – ICF1 – – OCF1B OCF1A TOV1 page 139 0x15 (0x35) TIFR0 – – – – – – OCF0A TOV0 page 105 0x14 (0x34) Reserved 0x13 (0x33) Reserved – – BBMB BBMA – – PUDB PUDA page 75 0x12 (0x32) PORTCR 0x11 (0x31) Reserved 0x10 (0x30) Reserved 0x0F (0x2F) Reserved 0x0E (0x2E) Re
26.
ATtiny87/ATtiny167 Mnemonics Operands Description Operation Flags LSR Rd Logical Shift Right Rd(n) ←Rd(n+1), Rd(7) ←0 Z,C,N,V #Clock 1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)←Rd(n),C←Rd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)←Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ←Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..
27. Ordering Information Ordering Code(3) Speed (MHz) Power Supply (V) ATtiny87-A15SZ ATtiny87-A15MZ Operation Range TG 16 2.7 - 5.5 PN ATtiny87-A15XZ 6G ATtiny167-A15SZ TG ATtiny167-A15MZ 16 2.7 - 5.5 ATtiny167-A15XZ Notes: Package(1)(2) PN –40° to +125°C –40° to +125°C 6G 1. Green and ROHS packaging. 2. Tape and Reel with Dry-pack delivery. 3.
ATtiny87/ATtiny167 28.
28.
ATtiny87/ATtiny167 28.
29. Errata 29.1 29.1.1 Errata Summary ATtiny87/167 RevC • Gain control of the crystal oscillator. • ‘Disable Clock Source’ command remains enabled. 29.1.2 ATtiny87/167 RevB (Date code >1208) • Gain control of the crystal oscillator. • ‘Disable Clock Source’ command remains enabled. • LIN Break Delimiter. 29.1.3 ATtiny167 RevA (Date code >1207) • CRC calculation of diagnostic frames in LIN 2.x. • Gain control of the crystal oscillator. • ‘Disable Clock Source’ command remains enabled.
ATtiny87/ATtiny167 – Once the RESPONSE is received or sent (having RxOK or TxOK as well as LERR), use the following function: void lin_wa_tail(void) LINCR = 0x00; { // It is not a RESET ! LINBTR = 0x00; LINCR = (0< 16 MHz) doesn’t latch its gain control (CKSEL/CSEL[2..0] bits): a.
3. ‘Disable Clock Source’ command remains enabled. In the Dynamic Clock Switch module, the ‘Disable Clock Source’ command remains running after disabling the targeted clock source (the clock source is set in the CLKSELR register). Problem fix / workaround. After a ‘Disable Clock Source’ command, reset the CLKCSR register writing 0x80.
ATtiny87/ATtiny167 6. LIN Break Delimitter In SLAVE MODE, a BREAK field detection error can occur under following conditions. The problem occurs if 2 conditions occur simultaneously: a. The DOMINANT part of the BREAK is (N+0.5)*Tbit long with N=13, 14,15, ... b. The RECESSIVE part of the BREAK (BREAK DELIMITER) is equal to 1*Tbit. (see note below) The BREAK_high is not detected, and the 2nd bit of the SYNC field is interpreted as the BREAK DELIMITER.
30. Revision History Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision. 30.1 Changes from 7728F - 05/10 to 7728G 06/10 1. Power on Reset values updated 30.2 Changes from 7728E - 04/10 to 7728F 05/10 1. Clock Characteristics updated 30.3 Changes from 7728D - 07/09 to 7728E 04/10 1. Ordering Information with new part numbers for silicon revision D updated 2. Errata updated 3.
Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg.
