Datasheet

ATtiny13

2535E–AVR–10/04

When an ADC conversion is complete, the result is found in these two registers.

When ADCL is read, the ADC Data Register is not updated until ADCH is read. Conse-

quently, if the result is left adjusted and no more than 8-bit precision is required, it is

sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH.

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is

read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared

(default), the result is right adjusted.

• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in “ADC Conversion

Result” on page 90.

ADC Control and Status

• Bits 7, 5..3 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13 and will always read as zero.

• Bits 2:0 – ADTS2:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source will

trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no

effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag.

Note that switching from a trigger source that is cleared to a trigger source that is set,

will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will

start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trig-

ger event, even if the ADC Interrupt Flag is set

Digital Input Disable Register

0 – DIDR0

• Bits 5..2 – ADC3D..ADC0D: ADC3..0 Digital Input Disable

Initial Value00000000

00000000

Bit 76543210

–

ACME – – – ADTS2 ADTS1 ADTS0 ADCSRB

Read/Write R R/W R R R R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 40. ADC Auto Trigger Source Selections

ADTS2 ADTS1 ADTS0 Trigger Source

0 0 0 Free Running mode

0 0 1 Analog Comparator

0 1 0 External Interrupt Request 0

0 1 1 Timer/Counter Compare Match A

1 0 0 Timer/Counter Overflow

1 0 1 Timer/Counter Compare Match B

1 1 0 Pin Change Interrupt Request

Bit 76543210

– – ADC0D ADC2D ADC3D ADC1D AIN1D AIN0D DIDR0

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value00000000