Datasheet

75
ATtiny13
2535E–AVR–10/04
Figure 38. Prescaler for Timer/Counter0
Note: 1. The synchronization logic on the input pins (T0) is shown in Figure 37.
General Timer/Counter
Control Register – GTCCR
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this
mode, the value that is written to the PSR10 bit is kept, hence keeping the Prescaler
Reset signal asserted. This ensures that the Timer/Counter is halted and can be config-
ured without the risk of advancing during configuration. When the TSM bit is written to
zero, the PSR10 bit is cleared by hardware, and the Timer/Counter start counting.
• Bit 0 – PSR10: Prescaler Reset Timer/Counter0
When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally
cleared immediately by hardware, except if the TSM bit is set.
PSR10
Clear
clk
T0
T0
clk
I/O
Synchronization
Bit 7 6 5 4 3 2 1 0
TSM
– – – – – – PSR10 GTCCR
Read/Write R/W R R R R R R R/W
Initial Value 0 0 0 0 0 0 0 0