Datasheet

120
ATtiny13
2535E–AVR–10/04
Notes: 1. All DC Characteristics contained in this data sheet are based on simulation and characterization of other AVR microcontrol-
lers manufactured in the same process technology. These values are preliminary values representing design targets, and
will be updated after characterization of actual silicon.
2. “Max” means the highest value where the pin is guaranteed to be read as low.
3. “Min” means the lowest value where the pin is guaranteed to be read as high.
4. Although each I/O port can sink more than the test conditions (20 mA at V
CC
= 5V, 10 mA at V
CC
= 3V for PB5, PB1:0, 10 mA
at V
CC
= 5V, 5 mA at V
CC
= 3V for PB4:2) under steady state conditions (non-transient), the following must be observed:
1] The sum of all IOL, for all ports, should not exceed 60 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
5. Although each I/O port can source more than the test conditions (20 mA at V
CC
= 5V, 10 mA at V
CC
= 3V for PB5, PB1:0, 10
mA at V
CC
= 5V, 5 mA at V
CC
= 3V for PB4:2) under steady state conditions (non-transient), the following must be observed:
1] The sum of all IOH, for all ports, should not exceed 60 mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
External Clock Drive Waveforms
Figure 61. External Clock Drive Waveforms
External Clock Drive
V
IL1
V
IH1
Table 57. External Clock Drive
Symbol Parameter
V
CC
= 1.8 - 5.5V V
CC
= 2.7 - 5.5V V
CC
= 4.5 - 5.5V
UnitsMin. Max. Min. Max. Min. Max.
1/t
CLCL
Clock Frequency 0 4 0 10 0 20 MHz
t
CLCL
Clock Period 1000 104 62.5 ns
t
CHCX
High Time 400 50 25 ns
t
CLCX
Low Time 400 50 25 ns
t
CLCH
Rise Time 2.0 1.6 0.5 µs
t
CHCL
Fall Time 2.0 1.6 0.5 µs
∆t
CLCL
Change in period from one clock cycle to the next 2 2 2 %