Datasheet

ATtiny13

2535E–AVR–10/04

This bit selects the voltage reference for the ADC, as shown in Table 37. If this bit is

changed during a conversion, the change will not go in effect until this conversion is

complete (ADIF in ADCSRA is set).

•

Bit 5 – ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data

adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately,

regardless of any ongoing conversions. For a complete description of this bit, see “The

ADC Data Register – ADCL and ADCH” on page 92.

• Bits 4:2 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13 and will always read as zero.

• Bits 1:0 – MUX1:0: Analog Channel Selection Bits

The value of these bits selects which combination of analog inputs are connected to the

ADC. See Table 38 for details.

If these bits are changed during a conversion, the

change will not go in effect until this conversion is complete (ADIF in ADCSRA is set).

ADC Control and Status

• Bit 7 – ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turn-

ing the ADC off while a conversion is in progress, will terminate this conversion.

• Bit 6 – ADSC: ADC Start Conversion

In Single Conversion mode, write this bit to one to start each conversion. In Free Run-

ning mode, write this bit to one to start the first conversion. The first conversion after

ADSC has been written after the ADC has been enabled, or if ADSC is written at the

same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal

13. This first conversion performs initialization of the ADC.

ADSC will read as one as long as a conversion is in progress. When the conversion is

complete, it returns to zero. Writing zero to this bit has no effect.

• Bit 5 – ADATE: ADC Auto Trigger Enable

Table 37. Voltage Reference Selections for ADC

REFS0 Voltage Reference Selection

used as analog reference.

1 Internal Voltage Reference.

Table 38. Input Channel Selections

MUX1..0 Single Ended Input

00 ADC0 (PB5)

01 ADC1 (PB2)

10 ADC2 (PB4)

11 ADC3 (PB3)

Bit 76543210

ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0