Datasheet

80
ATtiny13
2535E–AVR–10/04
Figure 40. Analog to Digital Converter Block Schematic
Operation The ADC converts an analog input voltage to a 10-bit digital value through successive
approximation. The minimum value represents GND and the maximum value represents
the voltage on V
CC
or an internal 1.1V reference voltage.
The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the
ADC input pins, can be selected as single ended inputs to the ADC.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage refer-
ence and input channel selections will not go into effect until ADEN is set. The ADC
does not consume power when ADEN is cleared, so it is recommended to switch off the
ADC before entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers,
ADCH and ADCL. By default, the result is presented right adjusted, but can optionally
be presented left adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to
read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content
of the data registers belongs to the same conversion. Once ADCL is read, ADC access
to data registers is blocked. This means that if ADCL has been read, and a conversion
completes before ADCH is read, neither register is updated and the result from the con-
ADC CONVERSION
COMPLETE IRQ
8-BIT DATA BUS
15 0
ADC MULTIPLEXER
SELECT (ADMUX)
ADC CTRL. & STATUS
REGISTER (ADCSRA)
ADC DATA REGISTER
(ADCH/ADCL)
ADIE
ADATE
ADSC
ADEN
ADIF
ADIF
MUX1
MUX0
ADPS0
ADPS1
ADPS2
CONVERSION LOGIC
10-BIT DAC
+
-
SAMPLE & HOLD
COMPARATOR
INTERNAL 1.1V
REFERENCE
MUX DECODER
V
CC
ADC3
ADC2
ADC1
ADC0
REFS1
ADLAR
CHANNEL SELECTION
ADC[9:0]
ADC MULTIPLEXER
OUTPUT
PRESCALER
INPUT
MUX
TRIGGER
SELECT
ADTS[2:0]
INTERRUPT
FLAGS
START