Datasheet

ATtiny13

2535E–AVR–10/04

EEPROM Data Memory The ATtiny13 contains 64 bytes of data EEPROM memory. It is organized as a separate

data space, in which single bytes can be read and written. The EEPROM has an endur-

ance of at least 100,000 write/erase cycles. The access between the EEPROM and the

CPU is described in the following, specifying the EEPROM Address Registers, the

EEPROM Data Register, and the EEPROM Control Register. For a detailed description

of Serial data downloading to the EEPROM, see page 106.

EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space.

The write access times for the EEPROM are given in Table 1. A self-timing function,

however, lets the user software detect when the next byte can be written. If the user

code contains instructions that write the EEPROM, some precautions must be taken. In

heavily filtered power supplies, V

is likely to rise or fall slowly on Power-up/down. This

causes the device for some period of time to run at a voltage lower than specified as

minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page

19 for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-

lowed. Refer to “Atomic Byte Programming” on page 17 and “Split Byte Programming”

on page 17 for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next

instruction is executed. When the EEPROM is written, the CPU is halted for two clock

cycles before the next instruction is executed.

EEPROM Address Register –

EEARL

• Bits 7..6 – Res: Reserved Bits

These bits are reserved bits in the ATtiny13 and will always read as zero.

• Bits 5..0 – EEAR5..0: EEPROM Address

The EEPROM Address Register – EEARL – specifies the EEPROM address in the 64

bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and

63. The initial value of EEARL is undefined. A proper value must be written before the

EEPROM may be accessed.

EEPROM Data Register –

EEDR

• Bits 7..0 – EEDR7..0: EEPROM Data

For the EEPROM write operation the EEDR Register contains the data to be written to

the EEPROM in the address given by the EEARL Register. For the EEPROM read oper-

ation, the EEDR contains the data read out from the EEPROM at the address given by

EEARL.

Bit 76543210

– – EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 X X X X X X

Bit 76543210

EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value X X X X X X X X