Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Througput at 20 MHz Non-volatile Program and Data Memories – 1K Byte of In-System Programmable Program Memory Flash Endurance: 10,000 Write/Erase Cycles – 64 Bytes In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – 64 Bytes Inter
Pin Configurations Figure 1.
ATtiny13 Block Diagram Figure 2. Block Diagram 8-BIT DATABUS STACK POINTER SRAM VCC PROGRAM COUNTER GND PROGRAM FLASH WATCHDOG OSCILLATOR CALIBRATED INTERNAL OSCILLATOR WATCHDOG TIMER TIMING AND CONTROL MCU CONTROL REGISTER MCU STATUS REGISTER TIMER/ COUNTER0 INSTRUCTION REGISTER INSTRUCTION DECODER CONTROL LINES GENERAL PURPOSE REGISTERS INTERRUPT UNIT X Y Z PROGRAMMING LOGIC ALU DATA EEPROM STATUS REGISTER ADC / ANALOG COMPARATOR DATA REGISTER PORT B DATA DIR. REG.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATtiny13 AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 3.
the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
ATtiny13 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATtiny13 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 5. Figure 5.
Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept.
ATtiny13 There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.
ATtiny13 AVR ATtiny13 Memories This section describes the different memories in the ATtiny13. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny13 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. In-System Reprogrammable Flash Program Memory The ATtiny13 contains 1K byte On-chip In-System Reprogrammable Flash memory for program storage.
SRAM Data Memory Figure 9 shows how the ATtiny13 SRAM Memory is organized. The lower 160 Data memory locations address both the Register File, the I/O memory and the internal data SRAM. The first 32 locations address the Register File, the next 64 locations the standard I/O memory, and the last 64 locations address the internal data SRAM.
ATtiny13 EEPROM Data Memory The ATtiny13 contains 64 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. For a detailed description of Serial data downloading to the EEPROM, see page 106.
EEPROM Control Register – EECR Bit 7 6 5 4 3 2 1 0 – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0 EECR • Bit 7 – Res: Reserved Bit This bit is reserved for future use and will always read as 0 in ATtiny13. For compatibility with future AVR devices, always write this bit to zero. After reading, mask out this bit. • Bit 6 – Res: Reserved Bit This bit is reserved in the ATtiny13 and will always read as zero.
ATtiny13 one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEARL Register. Atomic Byte Programming Using Atomic Byte Programming is the simplest mode.
The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATtiny13 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
I/O Memory The I/O space definition of the ATtiny13 is shown in “Register Summary” on page 157. All ATtiny13 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
ATtiny13 System Clock and Clock Options Clock Systems and their Distribution Figure 11 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 27. The clock systems are detailed below. Figure 11.
Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 2. Device Clocking Options Select(1) Device Clocking Option CKSEL1..0 Calibrated Internal RC Oscillator 01, 10 External Clock 00 128 kHz Internal Oscillator 11 Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.
ATtiny13 Calibrated Internal RC Oscillator The calibrated internal RC Oscillator provides an 9.6 MHz or 4.8 MHz clock. The frequency is the nominal value at 3V and 25°C. If the frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse must be programmed in order to divide the internal frequency by 8 during start-up. See “System Clock Prescaler” on page 25. for more details. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 4.
write may fail. Note that the Oscillator is intended for calibration to 9.6 MHz or 4.8 MHz. Tuning to other values is not guaranteed, as indicated in Table 6. Avoid changing the calibration value in large steps when calibrating the calibrated internal RC Oscillator to ensure stable operation of the MCU. A variation in frequency of more than 2% from one cycle to the next can lead to unpredictable behavior. Changes in OSCCAL-register should not exceed 0x20 for each calibration. Table 6.
ATtiny13 128 kHz Internal Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency is nominal at 3V and 25°C. This clock may be select as the system clock by programming the CKSEL Fuses to “11”. When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 8. Table 8. Start-up Times for the 128 kHz Internal Oscillator SUT1..
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of eight at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting.
ATtiny13 Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choice for low power applications. Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements.
Idle Mode When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow.
ATtiny13 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.
System Control and Reset Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 13 shows the reset logic.
ATtiny13 Figure 13. Reset Logic DATA BUS PORF BORF EXTRF WDRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [1..0] Pull-up Resistor SPIKE FILTER Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[1:0] SUT[1:0] Table 12. Reset Characteristics(1) Symbol Parameter Condition Power-on Reset Threshold Voltage (rising) TA = -40 - 85°C Power-on Reset Threshold Voltage (falling)(2) TA = -40 - 85°C VRST RESET Pin Threshold Voltage VCC = 1.
Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 12. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on.
ATtiny13 External Reset An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width (see Table 12) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay counter starts the MCU after the Time-out period – tTOUT – has expired. Figure 16.
Figure 17. Brown-out Reset During Operation VCC VBOT+ VBOT- RESET tTOUT TIME-OUT INTERNAL RESET Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 41 for details on operation of the Watchdog Timer. Figure 18.
ATtiny13 This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 0 – PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program.
Watchdog Timer ATtiny13 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 128kHz OSCILLATOR WATCHDOG RESET WDE OSC/2K OSC/4K OSC/8K OSC/16K OSC/32K OSC/64K OSC/128K OSC/256K OSC/512K OSC/1024K Figure 19.
ATtiny13 The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.
Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use. The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer.
ATtiny13 Watchdog Timer Control Register - WDTCR Bit 7 6 5 4 3 2 1 0 WDTIF WDTIE WDP3 WDCE WDE WDP2 WDP1 WDP0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 X 0 0 0 WDTCR • Bit 7 - WDTIF: Watchdog Timer Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDTIF is cleared by hardware when executing the corresponding interrupt handling vector.
. Table 17. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V 0 0 0 0 2K (2048) cycles 16 ms 0 0 0 1 4K (4096) cycles 32 ms 0 0 1 0 8K (8192) cycles 64 ms 0 0 1 1 16K (16384) cycles 0.125 s 0 1 0 0 32K (32768) cycles 0.25 s 0 1 0 1 64K (65536) cycles 0.5 s 0 1 1 0 128K (131072) cycles 1.0 s 0 1 1 1 256K (262144) cycles 2.0 s 1 0 0 0 512K (524288) cycles 4.
ATtiny13 Interrupts Interrupt Vectors in ATtiny13 This section describes the specifics of the interrupt handling as performed in ATtiny13. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 10. Table 18. Reset and Interrupt Vectors Vector No.
I/O Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
ATtiny13 Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 21 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 21.
Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur.
ATtiny13 Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge.
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ...
ATtiny13 when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).
Figure 24.
ATtiny13 Table 20 summarizes the function of the overriding signals. The pin and port indexes from Figure 24 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 20. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
MCU Control Register – MCUCR Bit 7 6 5 4 3 2 1 0 – PUD SE SM1 SM0 – ISC01 ISC00 Read/Write R R/W R/W R/W R/W R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bits 7, 2– Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bit 6 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
ATtiny13 Table 22. Overriding Signals for Alternate Functions in PB5..
Register Description for I/O-Ports Port B Data Register – PORTB Bit Port B Data Direction Register – DDRB Port B Input Pins Address – PINB 52 7 6 5 4 3 2 1 0 – – PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 – – DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 – – PINB5 P
ATtiny13 External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT5..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT5..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. Pin change interrupts PCI will trigger if any enabled PCINT5..0 pin toggles. The PCMSK Register control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT5..
External Interrupt registers MCU Control Register – MCUCR The External Interrupt Control Register A contains control bits for interrupt sense control. Bit 7 6 5 4 3 2 1 0 – PUD SE SM1 SM0 – ISC01 ISC00 Read/Write R R/W R/W R/W R/W R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.
ATtiny13 General Interrupt Mask Register – GIMSK Bit 7 6 5 4 3 2 1 0 – INT0 PCIE – – – – – Read/Write R R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 GIMSK • Bits 7, 4..0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
Pin Change Mask Register – PCMSK Bit 7 6 5 4 3 2 1 0 – – PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK • Bits 7, 6 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bits 5..0 – PCINT5..0: Pin Change Enable Mask 5..0 Each PCINT5..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT5..
ATtiny13 8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event management) and wave generation.
Compare pins (OC0A and OC0B). See “Output Compare Unit” on page 59. for details. The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt request. Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare Unit, in this case Compare Unit A or Compare Unit B.
ATtiny13 Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
ATtiny13 Compare Match Output Unit The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Generator uses the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next Compare Match. Also, the COM0x1:0 bits control the OC0x pin output source. Figure 29 shows a simplified schematic of the logic affected by the COM0x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM0x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
ATtiny13 to OCR0A is lower than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1).
Figure 31. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCn (COMnx1:0 = 2) OCn (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
ATtiny13 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5.
and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = ----------------N ⋅ 510 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
ATtiny13 Figure 34. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 35 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 35.
8-bit Timer/Counter Register Description Timer/Counter Control Register A – TCCR0A Bit 7 6 5 4 3 2 1 0 COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bits 7:6 – COM01A:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to.
ATtiny13 Table 28 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 28. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. 1 1 Set OC0A on Compare Match when up-counting.
Table 28 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 31. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting. 1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting. Note: Description 1.
ATtiny13 Timer/Counter Control Register B – TCCR0B Bit 7 6 5 4 3 2 1 0 FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode.
Table 33. Clock Select Bit Description (Continued) CS02 CS01 CS00 Description 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting.
ATtiny13 executed if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter Interrupt Flag Register – TIFR0. • Bit 2 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0 occurs, i.e.
Timer/Counter Prescaler The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a frequency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024. Prescaler Reset The prescaler is free running, i.e.
ATtiny13 Figure 38. Prescaler for Timer/Counter0 clk I/O Clear PSR10 T0 Synchronization clkT0 Note: General Timer/Counter Control Register – GTCCR 1. The synchronization logic on the input pins (T0) is shown in Figure 37. Bit 7 6 5 4 3 2 1 0 TSM – – – – – – PSR10 Read/Write R/W R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode.
Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 39.
ATtiny13 When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. • Bit 5 – ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles.
Analog Comparator Multiplexed Input It is possible to select any of the ADC3..0 pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX1..0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in Table 35.
ATtiny13 Analog to Digital Converter Features • • • • • • • • • • • • • 10-bit Resolution 0.5 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 13 - 260 µs Conversion Time Up to 15 kSPS at Maximum Resolution Four Multiplexed Single Ended Input Channels Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 1.
Figure 40. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] 15 TRIGGER SELECT ADC[9:0] ADPS0 ADPS1 ADIF ADPS2 ADATE ADEN 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL. & STATUS REGISTER (ADCSRA) ADSC MUX1 MUX0 ADLAR REFS1 ADC MULTIPLEXER SELECT (ADMUX) ADIE ADIF 8-BIT DATA BUS MUX DECODER CHANNEL SELECTION PRESCALER VCC START CONVERSION LOGIC INTERNAL 1.
ATtiny13 version is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost. Starting a Conversion A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.
Prescaling and Conversion Timing Figure 42. ADC Prescaler ADEN START Reset 7-BIT ADC PRESCALER CK/128 CK/64 CK/32 CK/16 CK/8 CK/4 CK/2 CK ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.
ATtiny13 Figure 43. ADC Timing Diagram, First Conversion (Single Conversion Mode) Next Conversion First Conversion Cycle Number 1 2 12 13 14 16 15 17 18 19 20 21 22 23 24 25 1 2 3 ADC Clock ADEN ADSC ADIF Sign and MSB of Result ADCH LSB of Result ADCL MUX and REFS Update Conversion Complete Sample & Hold MUX and REFS Update Figure 44.
Figure 46. ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number 11 12 Next Conversion 13 1 2 3 4 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete MUX and REFS Update Table 36. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 25 Normal conversions 1.5 13 2 13.
ATtiny13 Changing Channel or Reference Selection The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC.
ADC Voltage Reference The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either VCC, or internal 1.1V reference, or external AREF pin. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result.
ATtiny13 Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 47. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path).
Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. 2. Use the ADC noise canceler function to reduce induced noise from the CPU. 3.
ATtiny13 Figure 49. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 50.
Figure 51. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 ADC Conversion Result VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code.
ATtiny13 This bit selects the voltage reference for the ADC, as shown in Table 37. If this bit is changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). Table 37. Voltage Reference Selections for ADC • REFS0 Voltage Reference Selection 0 VCC used as analog reference. 1 Internal Voltage Reference. Bit 5 – ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB. • Bit 4 – ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.
ATtiny13 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 When an ADC conversion is complete, the result is found in these two registers. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers.
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC3..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
ATtiny13 debugWIRE On-chip Debug System Features • • • • • • • • • • Overview The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the program flow, execute AVR instructions in the CPU and to program the different non-volatile memories. Physical Interface When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE system within the target device is activated.
Software Break Points • Capacitors inserted on the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a Break Point in AVR Studio ® will insert a BREAK instruction in the Program memory. The instruction replaced by the BREAK instruction will be stored.
ATtiny13 Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The Program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
Addressing the Flash During SelfProgramming The Z-pointer is used to address the SPM commands. Bit 15 14 13 12 11 10 9 8 ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 7 6 5 4 3 2 1 0 Since the Flash is organized in pages (see Table 46 on page 105), the Program Counter can be treated as having two different sections.
ATtiny13 Store Program Memory Control and Status Register – SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to control the Program memory operations. Bit 7 6 5 4 3 2 1 0 – – – CTPB RFLB PGWRT PGERS SELFPRGEN Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPMCSR • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and always read as zero.
EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software.
ATtiny13 Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly.
Memory Programming This section describes the different methods for Programming the ATtiny13 memories. Program And Data Memory Lock Bits The ATtiny13 provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional security listed in Table 43. The Lock bits can only be erased to “1” with the Chip Erase command. Program memory can be read out via the debugWIRE interface when the DWEN fuse is programmed, even if the Lock Bits are set.
ATtiny13 Fuse Bytes The ATtiny13 has two Fuse bytes. Table 44 and Table 45 describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 44.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
ATtiny13 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device.
Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 48 on page 106, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface. Figure 54.
ATtiny13 Serial Programming Algorithm When writing serial data to the ATtiny13, data is clocked on the rising edge of SCK. When reading data from the ATtiny13, data is clocked on the falling edge of SCK. See Figure 55 and Figure 56 for timing details. To program and verify the ATtiny13 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 50): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”.
. Table 49. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 4.0 ms tWD_ERASE 4.0 ms tWD_FUSE 4.5 ms Figure 55.
ATtiny13 Table 50. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. Read Program Memory 0010 H000 0000 000a bbbb bbbb oooo oooo Read H (high or low) data o from Program memory at word address a:b.
Serial Programming Characteristics Figure 56. Serial Programming Timing MOSI tSHOX tOVSH SCK tSLSH tSHSL MISO tSLIV Table 51. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 1.8 - 5.5V (Unless Otherwise Noted) Symbol Parameter 1/tCLCL Oscillator Frequency (ATtiny13V) Oscillator Period (ATtiny13V) tCLCL Typ 0 Max Units 1 MHz 1,000 1/tCLCL Oscillator Frequency (ATtiny13L, VCC = 2.7 5.5V) 0 tCLCL Oscillator Period (ATtiny13L, VCC = 2.7 - 5.5V) 104 ns 9.
ATtiny13 High-voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data memory, Lock bits and Fuse bits in the ATtiny13. Figure 57. High-voltage Serial Programming +11.5 - 12.5V SERIAL CLOCK INPUT +1.8 - 5.5V PB5 (RESET) VCC PB3 (CLKI) PB2 SCK PB1 MISO PB0 MOSI GND Table 52.
High-voltage Serial Programming Algorithm To program and verify the ATtiny13 in the High-voltage Serial Programming mode, the following sequence is recommended (See instruction formats in Table 55): Enter High-voltage Serial Programming Mode The following algorithm puts the device in High-voltage Serial Programming mode: 1. Apply 4.5 - 5.5V between VCC and GND. 2. Set RESET pin to “0” and toggle SCI at least six times. 3. Set the Prog_enable pins listed in Table 53 to “000” and wait at least 100 ns. 4.
ATtiny13 Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are not reset until the Program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are re-programmed. Note: 1. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed. 1. Load command “Chip Erase” (see Table 55). 2. Wait after Instr. 3 until SDO goes high for the “Chip Erase” cycle to finish. 3.
Programming the Flash The Flash is organized in pages, see Table 50 on page 109. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: 1. Load Command “Write Flash” (see Table 55). 2. Load Flash Page Buffer. 3. Load Flash High Address and Program Page. Wait after Instr. 3 until SDO goes high for the “Page Programming” cycle to finish. 4.
ATtiny13 Programming the EEPROM The EEPROM is organized in pages, see Table 51 on page 110. When programming the EEPROM, the data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM Data memory is as follows (refer to Table 55): 1. Load Command “Write EEPROM”. 2. Load EEPROM Page Buffer. 3. Program EEPROM Page. Wait after Instr. 2 until SDO goes high for the “Page Programming” cycle to finish. 4.
Table 55. High-voltage Serial Programming Instruction Set for ATtiny13 Instruction Format Instruction Chip Erase Load “Write Flash” Command Load Flash Page Buffer Instr.1/5 Instr.2/6 Instr.
ATtiny13 Table 55. High-voltage Serial Programming Instruction Set for ATtiny13 (Continued) Instruction Format Instruction Load “Read EEPROM” Command Read EEPROM Byte Write Fuse Low Bits Instr.
High-voltage Serial Programming Characteristics Figure 60. High-voltage Serial Programming Timing SDI (PB0), SII (PB1) tIVSH SCI (PB3) tSHIX tSLSH tSHSL SDO (PB2) tSHOV Table 56. High-voltage Serial Programming Characteristics VCC = 5.
ATtiny13 Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Notes: 1. All DC Characteristics contained in this data sheet are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual silicon. 2. “Max” means the highest value where the pin is guaranteed to be read as low. 3. “Min” means the lowest value where the pin is guaranteed to be read as high. 4.
ATtiny13 Maximum Speed vs. VCC Maximum frequency is dependent on VCC. As shown in Figure 62 and Figure 63, the Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V. Figure 62. Maximum Frequency vs. VCC, ATtiny13V 10 MHz Safe Operating Area 4 MHz 1.8V 2.7V 5.5V Figure 63. Maximum Frequency vs. VCC, ATtiny13 20 MHz 10 MHz Safe Operating Area 2.7V 4.5V 5.
ADC Characteristics – Preliminary Data Table 58. ADC Characteristics, Single Ended Channels. -40°C - 85°C Symbol Parameter Resolution Min(1) Single Ended Conversion Units 10 Bits LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1 MHz 3 LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode 1.5 LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1 MHz Noise Reduction Mode 2.
ATtiny13 ATtiny13 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
Figure 65. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 20MHz 14 5.5 V 12 5.0 V ICC (mA) 10 4.5 V 8 6 4.0 V 3.3 V 2.7 V 4 2 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 66. Active Supply Current vs. VCC (Internal RC Oscillator, 9.6 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 9.6 MHz 8 85 °C -40 °C 7 6 25 °C ICC (mA) 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny13 Figure 67. Active Supply Current vs. VCC (Internal RC Oscillator, 4.8 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4.8 MHz 4.5 25 °C -40 °C 85 °C 4 3.5 ICC (mA) 3 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 68. Active Supply Current vs. VCC (Internal WDT Oscillator, 128 kHz) ACTIVE SUPPLY CURRENT vs. V CC INTERNAL WD OSCILLATOR, 128 KHz 0.14 -40 °C 25 °C 85 °C 0.12 ICC (mA) 0.1 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 69. Active Supply Current vs. VCC (32 kHz External Clock) ACTIVE SUPPLY CURRENT vs. V CC 32 kHz EXTERNAL CLOCK 0.04 25 °C 0.035 85 °C 0.03 ICC (mA) 0.025 0.02 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 70. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY (0.1 - 1.0 MHz) ICC (mA) 0.9 0.8 5.5 V 0.7 5.0 V 0.6 4.5 V 0.5 4.0 V 0.4 3.3 V 0.3 2.7 V 0.2 1.8 V 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.
ATtiny13 Figure 71. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20MHz 5 ICC (mA) 4.5 4 5.5 V 3.5 5.0 V 3 4.5 V 2.5 2 1.5 4.0 V 1 3.3 V 2.7 V 0.5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 72. Idle Supply Current vs. VCC (Internal RC Oscillator, 9.6 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 9.6 MHz 2.5 85 °C 25 °C -40 °C ICC (mA) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 73. Idle Supply Current vs. VCC (Internal RC Oscillator, 4.8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4.8 MHz 1.2 85 °C 25 °C -40 °C 1 ICC (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 74. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL WD OSCILLATOR, 128 KHz 0.035 -40 °C 25 °C 85 °C 0.03 ICC (mA) 0.025 0.02 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny13 Figure 75. Idle Supply Current vs. VCC (32 kHz External Clock) IDLE SUPPLY CURRENT vs. VCC 32kHz EXTERNAL CLOCK 10 9 85 °C 8 25 °C -40 °C ICC (uA) 7 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-Down Supply Current Figure 76. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 1.8 1.6 85 ˚C 1.4 ICC (uA) 1.2 1 0.8 -40 ˚C 25 ˚C 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 77. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 10 -40 ˚C 85 ˚C 25 ˚C 9 8 ICC (uA) 7 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Pin Pull-up Figure 78. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs.
ATtiny13 Figure 79. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 2.7 80 25 ˚C 85 ºC 70 60 -40 ˚C IOP (uA) 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 80. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs.
Figure 81. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 2.7V 60 25 ˚C -40 ˚C 50 85 ˚C IRESET (uA) 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Pin Driver Strength Figure 82. I/O Pin Source Current vs. Output Voltage (Low Power Ports, VCC = 5V) I/O PIN SOURCE CURRENT vs.
ATtiny13 Figure 83. I/O Pin Source Current vs. Output Voltage (Low Power Ports, VCC = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE LOW POWER PORTS, VCC = 2.7V 25 -40 °C IOH (mA) 20 25 °C 85 °C 15 10 5 0 0 0.5 1 1.5 2 2.5 3 VOH (V) Figure 84. I/O Pin Source Current vs. Output Voltage (Low Power Ports, VCC = 1.8V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE LOW POWER PORTS, VCC = 1.8V 7 -40 ˚C 25 ˚C 6 85 ˚C IOH (mA) 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 85. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, VCC = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE LOW POWER PORTS, VCC = 5V 50 45 -40 ˚C 40 25 ˚C IOL (mA) 35 85 ˚C 30 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 86. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, VCC = 2.7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Low Power Ports, VCC = 2.7V 20 18 -40 ˚C 16 25 ˚C IOL (mA) 14 85 ˚C 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.
ATtiny13 Figure 87. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, VCC = 1.8V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE LOW POWER PORTS, 1.8V 7 6 -40 ˚C IOL (mA) 5 25 ˚C 85 ˚C 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) Figure 88. I/O Pin Source Current vs. Output Voltage (VCC = 5V) I/O PIN SOURCE CURRENT vs.
Figure 89. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 2.7V 35 30 -40 ˚C 25 ˚C 25 IOH (mA) 85 ˚C 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 VOH (V) Figure 90. I/O Pin Source Current vs. Output Voltage (VCC = 1.8V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 1.8V 10 -40 ˚C 9 25 ˚C 8 85 ˚C IOH (mA) 7 6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATtiny13 Figure 91. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE VCC = 5V 100 90 -40 ˚C 80 25 ˚C IOL (mA) 70 85 ˚C 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 92. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE VCC = 2.7V 40 35 -40 ˚C 30 25 ˚C IOL (mA) 25 85 ˚C 20 15 10 5 0 0 0.5 1 1.5 2 2.
Figure 93. I/O Pin Sink Current vs. Output Voltage (VCC = 1.8V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE VCC = 1.8V 14 12 -40 ˚C IOL (mA) 10 25 ˚C 85 ˚C 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) Figure 94. Reset Pin as I/O - Source Current vs. Output Voltage (VCC = 5V) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 5V 1.6 1.4 -40 ˚C 1.2 25 ˚C IOH (mA) 1 85 ˚C 0.8 0.6 0.4 0.
ATtiny13 Figure 95. Reset Pin as I/O - Source Current vs. Output Voltage (VCC = 2.7V) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 2.7V 2.5 -40 ˚C 2 IOH (mA) 25 ˚C 85 ˚C 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 3 VOH (V) Figure 96. Reset Pin as I/O - Source Current vs. Output Voltage (VCC = 1.8V) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 1.8V 2.5 -40 °C 2 IOH (mA) 25 °C 1.5 1 85 °C 0.5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 97. Reset Pin as I/O - Sink Current vs. Output Voltage (VCC = 5V) RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE VCC = 5V 14 -40 ˚C 12 25 ˚C IOL (mA) 10 85 ˚C 8 6 4 2 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 98. Reset Pin as I/O - Sink Current vs. Output Voltage (VCC = 2.7V) RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE VCC = 2.7V 4.5 -40 ˚C 4 3.5 25 ˚C IOL (mA) 3 85 ˚C 2.5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.
ATtiny13 Figure 99. Reset Pin as I/O - Sink Current vs. Output Voltage (VCC = 1.8V) RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE VCC = 1.8V 1.6 1.4 -40 ˚C 1.2 25 ˚C IOL (mA) 1 85 ˚C 0.8 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) Pin Thresholds and Hysteresis Figure 100. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as '1') I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 3 85 ˚C 25 ˚C 2.5 -40 ˚C Threshold (V) 2 1.5 1 0.5 0 1.
Figure 101. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as '0') I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 3 85 ˚C 25 ˚C -40 ˚C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 5 5.5 VCC (V) Figure 102. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC 0.45 0.4 -40 ºC Input Hysteresis (V) 0.35 0.3 25 ºC 0.25 0.2 85 ºC 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.
ATtiny13 Figure 103. Reset Pin as I/O - Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as '1') RESET PIN AS I/O - THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 3 2.5 Threshold (V) 2 -40 ˚C 1.5 25 ˚C 1 85 ˚C 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 104. Reset Pin as I/O - Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as '0') RESET PIN AS I/O - THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 2.5 Threshold (V) 2 1.5 85 ˚C 1 25 ˚C 0.5 -40 ˚C 0 1.5 2 2.5 3 3.
Figure 105. Reset Pin as I/O - Pin Hysteresis vs. VCC RESET PIN AS IO - PIN HYSTERESIS vs. VCC 0.7 0.6 -40 ºC Input Hysteresis (V) 0.5 25 ºC 0.4 85 ºC 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 106. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as '1') RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 2.5 Threshold (V) 2 1.5 -40 ˚C 1 85 ˚C 25 ˚C 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny13 Figure 107. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as '0') RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 2.5 Threshold (V) 2 1.5 1 0.5 85 ˚C 25 ˚C -40 ˚C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 108. Reset Input Pin Hysteresis vs. VCC RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 0.5 -40 ºC Threshold (V) 0.4 0.3 85 ºC 0.2 25 ºC 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
BOD Thresholds and Analog Comparator Offset Figure 109. BOD Thresholds vs. Temperature (BODLEVEL is 4.3V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.3V 4.5 Rising VCC Threshold (V) 4.4 4.3 Falling VCC 4.2 -60 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 110. BOD Thresholds vs. Temperature (BODLEVEL is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 2.7V 2.9 Rising V CC Threshold (V) 2.8 2.7 Falling V CC 2.
ATtiny13 Figure 111. BOD Thresholds vs. Temperature (BODLEVEL is 1.8V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 1.8V 1.9 Rising V CC Threshold (V) 1.85 1.8 Falling V CC 1.75 -60 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 112. Bandgap Voltage vs. VCC BANDGAP VOLTAGE vs. VCC 1.06 Bandgap Voltage (V) 1.04 1.02 85ºC 25ºC 1 0.98 -40ºC 0.96 0.94 0.92 1.5 2.5 3.5 4.5 5.
Figure 113. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) ANALOG COMPARATOR OFFSET vs. COMMON MODE VOLTAGE VCC = 5V 0.008 85 °C 25 °C -40 °C Comparator Offset Voltage (V) 0.007 0.006 0.005 0.004 0.003 0.002 0.001 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Voltage (V) Figure 114. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC= 2.7V) ANALOG COMPARATOR OFFSET vs. COMMON MODE VOLTAGE VCC = 2.7V 0.003 85 °C Comparator Offset Voltage (V) 0.0025 25 °C 0.
ATtiny13 Internal Oscillator Speed Figure 115. Calibrated 9.6 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 9.6 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 10.3 10.1 9.9 FRC (MHz) 9.7 9.5 5.5 V 9.3 4.5 V 9.1 2.7 V 8.9 1.8 V 8.7 8.5 -60 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 116. Calibrated 9.6 MHz RC Oscillator Frequency vs. VCC CALIBRATED 9.6 MHz RC OSCILLATOR FREQUENCY vs. VCC 11 10.5 85 ˚C FRC (MHz) 10 25 ˚C 9.5 -40 ˚C 9 8.5 8 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 117. Calibrated 9.6 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 9.6MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 18 25 ˚C 16 FRC (MHz) 14 12 10 8 6 4 2 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 OSCCAL VALUE Figure 118. Calibrated 4.8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 5.1 5 F RC (MHz) 4.9 4.8 1.8 V 4.7 5.5 V 4.0 V 4.6 2.7 V 4.
ATtiny13 Figure 119. Calibrated 4.8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs. VCC 5.2 85 ˚C FRC (MHz) 5 4.8 25 ˚C -40 ˚C 4.6 4.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 120. Calibrated 4.8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs.
Figure 121. 128 kHz Watchdog Oscillator Frequency vs. VCC 128 kHz WATCHDOG OSCILLATOR FREQUENCY vs. VCC 120 -40 ˚C FRC (kHz) 115 25 ˚C 110 85 ˚C 105 100 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 122. 128 kHz Watchdog Oscillator Frequency vs. Temperature 128 kHz WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 118 116 114 FRC (kHz) 112 110 1.8 V 108 2.7 V 4.0 V 5.
ATtiny13 Current Consumption of Peripheral Units Figure 123. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC 35 -40 ˚C 25 ˚C 85 ˚C 30 ICC (uA) 25 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 124. ADC Current vs. VCC ADC CURRENT vs. VCC 350 -40 ˚C 300 25 ˚C ICC (uA) 250 85 ˚C 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 125. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 140 ICC (uA) -40 ˚C 120 25 ˚C 100 85 ˚C 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 5 5.5 VCC (V) Figure 126. Programming Current vs. VCC PROGRAMMING CURRENT vs. Vcc 4 3.5 3 ICC (mA) 2.5 2 1.5 1 -40 °C 25 °C 0.5 85 °C 0 1.5 2 2.5 3 3.5 4 4.
ATtiny13 Current Consumption in Reset and Reset Pulse width Figure 127. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current through the Reset Pull-up) RESET SUPPLY CURRENT vs. VCC 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP 0.14 5.5 V 0.12 5.0 V ICC (mA) 0.1 4.5 V 0.08 4.0 V 0.06 3.3 V 2.7 V 0.04 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 128. Reset Supply Current vs.
Figure 129. Reset Pulse Width vs. VCC RESET PULSE WIDTH vs. V CC 2500 Pulsewidth (ns) 2000 1500 1000 500 85 ºC 25 ºC -40 ºC 0 1.8 2.1 2.5 2.7 3 3.3 3.5 4 4.5 5 5.
ATtiny13 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3F SREG I T H S V N Z C page 7 0x3E Reserved – – – – – – – – 0x3D SPL SP[7:0] 0x3C Reserved – 0x3B GIMSK – INT0 PCIE – – – – – page 55 0x3A GIFR – INTF0 PCIF – – – – – page 55 0x39 TIMSK0 – – – – OCIE0B OCIE0A TOIE0 – page 72 0x38 TIFR0 – – – – OCF0B OCF0A TOV0 – page 73 0x37 SPMCSR – – – CTPB RFLB PGWRT PGERS SELFPRGEN page
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them.
ATtiny13 Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Regi
Mnemonics Operands Description Operation Flags #Clocks ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..
ATtiny13 Ordering Information Speed (MHz)(3) 10 20 Notes: Ordering Code Package(1) 1.8 - 5.5 ATtiny13V-10PI ATtiny13V-10PU(2) ATtiny13V-10SI ATtiny13V-10SU(2) ATtiny13V-10SSI ATtiny13V-10SSU(2) ATtiny13V-10MI ATtiny13V-10MU(2) 8P3 8P3 8S2 8S2 S8S1 S8S1 20M1 20M1 Industrial (-40°C to 85°C) 2.7 - 5.
Packaging Information 8P3 E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A SYMBOL MIN NOM A b2 b3 b 4 PLCS Side View L 0.210 NOTE 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 D1 0.005 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 0.100 BSC eA 0.300 BSC 0.115 3 3 e L Notes: MAX 0.130 4 0.150 2 1.
ATtiny13 8S2 C 1 E E1 L N Top View ∅ End View e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D Side View NOM MAX NOTE A 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 5 C 0.15 0.35 5 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 ∅ 0˚ e Notes: 1. 2. 3. 4. 5. MIN 2, 3 8˚ 1.27 BSC 4 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs are not included.
S8S1 1 E1 E N Top View e b A A1 D Side View C L End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX E 5.79 6.20 E1 3.81 3.99 A 1.35 1.75 A1 0.1 0.25 D 4.80 4.98 C 0.17 0.25 b 0.31 0.51 L 0.4 e NOTE 1.27 1.27 BSC 0o 8o Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc. 7/28/03 R 164 2325 Orchard Parkway San Jose, CA 95131 TITLE S8S1, 8-lead, 0.
ATtiny13 20M1 D 1 Pin 1 ID 2 SIDE VIEW E 3 TOP VIEW A2 D2 A1 A 0.08 1 2 Pin #1 Notch (0.20 R) 3 COMMON DIMENSIONS (Unit of Measure = mm) E2 b L e BOTTOM VIEW SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 – 0.01 0.05 A2 b 0.18 D D2 E2 L 0.23 0.30 4.00 BSC 2.45 2.60 2.75 4.00 BSC 2.45 e Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. NOTE 0.20 REF E Note: C 2.60 2.75 0.50 BSC 0.35 0.40 0.
Errata The revision letter in this section refers to the revision of the ATtiny13 device. ATtiny13 Rev. D • EEPROM can not be written below 1.9 Volt 1. EEPROM can not be written below 1.9 Volt Writing the EEPROM at VCC below 1.9 volts might fail. Problem Fix/Workaround Do not write the EEPROM when VCC is below 1.9 volts. ATtiny13 Rev.
ATtiny13 4. debugWIRE communication not blocked by lock-bits When debugWIRE on-chip debug is enabled (DWEN = 0), the contents of program memory and EEPROM data memory can be read even if the lock-bits are set to block further reading of the device. Problem fix/ Workaround Do not ship products with on-chip debug of the tiny13 enabled. 5.
Datasheet Revision History Changes from Rev. 2535D-04/04 to Rev. 2535E-10/04 Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision. 1. 2. 3. 2. 4. 5. 6. 7. 8. 9. 10. 11. 12. Changes from Rev. 2535C-02/04 to Rev. 2535D-04/04 Changes from Rev. 2535B-01/04 to Rev. 2535C-02/04 Changes from Rev. 2535A-06/03 to Rev. 2535B-01/04 1. 2. 3. 4.
ATtiny13 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Updated Figure 54 on page 106 and Figure 57 on page 111. Updated registers “MCU Control Register – MCUCR” on page 50, “Timer/Counter Control Register B – TCCR0B” on page 71 and “Digital Input Disable Register 0 – DIDR0” on page 78. Updated Absolute Maximum Ratings and DC Characteristics in “Electrical Characteristics” on page 119. Added “Maximum Speed vs. VCC” on page 121 Updated “ADC Characteristics – Preliminary Data” on page 122.
ATtiny13 2535E–AVR–10/04
ATtiny13 Table of Contents Features................................................................................................ 1 Pin Configurations............................................................................... 2 Overview............................................................................................... 2 Block Diagram ...................................................................................................... 3 Pin Descriptions....................................
Interrupt Vectors in ATtiny13 .............................................................................. 41 I/O Ports.............................................................................................. 42 Introduction ......................................................................................................... Ports as General Digital I/O ................................................................................ Alternate Port Functions ......................................
ATtiny13 Memory Programming..................................................................... 102 Program And Data Memory Lock Bits .............................................................. Fuse Bytes........................................................................................................ Signature Bytes ................................................................................................ Calibration Byte .....................................................................
ATtiny13 Rev. A................................................................................................ 167 Datasheet Revision History ............................................................ 168 Changes from Rev. 2535D-04/04 to Rev. 2535E-10/04 ................................... Changes from Rev. 2535C-02/04 to Rev. 2535D-04/04................................... Changes from Rev. 2535B-01/04 to Rev. 2535C-02/04 ................................... Changes from Rev. 2535A-06/03 to Rev.
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