Datasheet

9
ATtiny11/12
1006D–AVR–07/03
Figure 6. The ATtiny11/12 AVR RISC Architecture
A flexible interrupt module has its control registers in the I/O space with an additional
global interrupt enable bit in the status register. All the different interrupts have a sepa-
rate interrupt vector in the interrupt vector table at the beginning of the
program memory. The different interrupts have priority in accordance with their interrupt
vector position. The lower the interrupt vector address, the higher the priority.
General-purpose
Register File
Figure 7 shows the structure of the 32 general-purpose registers in the CPU.
Figure 7. AVR CPU General-purpose Working Registers
All the register operating instructions in the instruction set have direct- and single-cycle
access to all registers. The only exception is the five constant arithmetic and logic
instructions SBCI, SUBI, CPI, ANDI, and ORI between a constant and a register and the
LDI instruction for load-immediate constant data. These instructions apply to the second
half of the registers in the register file – R16..R31. The general SBC, SUB, CP, AND,
512 x 16
Program
Flash
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General-
purpose
Registers
ALU
Direct Addressing
Status
and Test
Control
Registers
Interrupt
Unit
8-bit
Timer/Counter
Watchdog
Timer
Analog
Comparator
6
I/O Lines
8-bit Data Bus
SPI Unit
(ATtiny12 only)
64 x 8 EEPROM
(ATtiny12 only)
70
R0
R1
R2
General- …
purpose …
Working R28
Registers R29
R30 (Z-register low byte)
R31 (Z-register high byte)