Datasheet
Table Of Contents
- Features
- Pin Configuration
- Description
- Architectural Overview
- General-purpose Register File
- ALU – Arithmetic Logic Unit
- Flash Program Memory
- Program and Data Addressing Modes
- Subroutine and Interrupt Hardware Stack
- EEPROM Data Memory
- Memory Access and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- ATtiny12 Internal Voltage Reference
- Interrupt Handling
- Sleep Modes for the ATtiny11
- Sleep Modes for the ATtiny12
- ATtiny12 Calibrated Internal RC Oscillator
- Timer/Counter0
- Watchdog Timer
- ATtiny12 EEPROM Read/Write Access
- Analog Comparator
- I/O Port B
- Memory Programming
- Program (and Data) Memory Lock Bits
- Fuse Bits in ATtiny11
- Fuse Bits in ATtiny12
- Signature Bytes
- Calibration Byte in ATtiny12
- Programming the Flash and EEPROM
- High-voltage Serial Programming
- High-voltage Serial Programming Algorithm
- High-voltage Serial Programming Characteristics
- Low-voltage Serial Downloading (ATtiny12 only)
- Low-voltage Serial Programming Characteristics
- Electrical Characteristics
- Register Summary ATtiny11
- Register Summary ATtiny12
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Data Sheet Change Log for ATtiny11/12
- Table of Contents
82
ATtiny11/12
1006D–AVR–07/03
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.
Register Summary ATtiny12
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
$3F SREG I T H S V N Z C page 14
$3E Reserved
$3D Reserved
$3C Reserved
$3B GIMSK - INT0 PCIE - - - - - page 25
$3A GIFR
-INTF0PCIF - - - - - page 26
$39 TIMSK
- - - - - -TOIE0- page 26
$38 TIFR
- - - - - -TOV0- page 27
$37 Reserved
$36 Reserved
$35 MCUCR - PUD SE SM - - ISC01 ISC00 page 29
$34 MCUSR
- - - - WDRF BORF EXTRF PORF page 24
$33 TCCR0
- - - - - CS02 CS01 CS00 page 34
$32 TCNT0 Timer/Counter0 (8 Bit) page 35
$31 OSCCAL Oscillator Calibration Register page 32
$30 Reserved
... Reserved
$22 Reserved
$21 WDTCR - - - WDTOE WDE WDP2 WDP1 WDP0 page 36
$20 Reserved
$1F Reserved
$1E EEAR - - EEPROM Address Register page 38
$1D EEDR EEPROM Data Register page 38
$1C EECR
- - - - EERIE EEMWE EEWE EERE page 38
$1B Reserved
$1A Reserved
$19 Reserved
$18 PORTB - - - PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 44
$17 DDRB
- - DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 44
$16 PINB
- - PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 44
$15 Reserved
... Reserved
$0A Reserved
$09 Reserved
$08 ACSR ACD AINBG ACO ACI ACIE - ACIS1 ACIS0 page 41
... Reserved
$00 Reserved