Datasheet
Table Of Contents
- Features
- Pin Configuration
- Description
- Architectural Overview
- General-purpose Register File
- ALU – Arithmetic Logic Unit
- Flash Program Memory
- Program and Data Addressing Modes
- Subroutine and Interrupt Hardware Stack
- EEPROM Data Memory
- Memory Access and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- ATtiny12 Internal Voltage Reference
- Interrupt Handling
- Sleep Modes for the ATtiny11
- Sleep Modes for the ATtiny12
- ATtiny12 Calibrated Internal RC Oscillator
- Timer/Counter0
- Watchdog Timer
- ATtiny12 EEPROM Read/Write Access
- Analog Comparator
- I/O Port B
- Memory Programming
- Program (and Data) Memory Lock Bits
- Fuse Bits in ATtiny11
- Fuse Bits in ATtiny12
- Signature Bytes
- Calibration Byte in ATtiny12
- Programming the Flash and EEPROM
- High-voltage Serial Programming
- High-voltage Serial Programming Algorithm
- High-voltage Serial Programming Characteristics
- Low-voltage Serial Downloading (ATtiny12 only)
- Low-voltage Serial Programming Characteristics
- Electrical Characteristics
- Register Summary ATtiny11
- Register Summary ATtiny12
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Data Sheet Change Log for ATtiny11/12
- Table of Contents

58
ATtiny11/12
1006D–AVR–07/03
Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low.
2. “Min” means the lowest value where the pin is guaranteed to be read as high.
3. Although each I/O port can sink more than the test conditions (20 mA at V
CC
= 5V, 10 mA at V
CC
= 3V) under steady state
conditions (non-transient), the following must be observed:
1] The sum of all I
OL
, for all ports, should not exceed 100 mA.
If I
OL
exceeds the test condition, V
OL
may exceed the related specification.
Pins are not guaranteed to sink current greater than the listed test conditions.
4. Although each I/O port can source more than the test conditions (3 mA at V
CC
= 5V, 1.5 mA at V
CC
= 3V) under steady state
conditions (non-transient), the following must be observed:
1] The sum of all I
OH
, for all ports, should not exceed 100 mA.
If I
OH
exceeds the test condition, V
OH
may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
5. Minimum V
CC
for Power-down is 1.5V. (On ATtiny12: only with BOD disabled)
I
CC
Power Supply Current
Active 1 MHz, V
CC
= 3V
(ATtiny12V)
1.0 mA
Active 2 MHz, V
CC
= 3V
(ATtiny11L)
2.0 mA
Active 4 MHz, V
CC
= 3V
(ATtiny12L)
2.5 mA
Active 6 MHz, V
CC
= 5V
(ATtiny11)
10 mA
Active 8 MHz, V
CC
= 5V
(ATtiny12)
10 mA
Idle 1 MHz, V
CC
= 3V
(ATtiny12V)
0.4 mA
Idle 2 MHz, V
CC
= 3V
(ATtiny11L)
0.5 mA
Idle 4 MHz, V
CC
= 3V
(ATtiny12L)
1.0 mA
Idle 6 MHz, V
CC
= 5V
(ATtiny11)
2.0 mA
Idle 8 MHz, V
CC
= 5V
(ATtiny12)
3.5 mA
Power Down
(5)
, V
CC
= 3V,
WDT enabled
9.0 15 µA
Power Down
(5)
, V
CC
= 3V.
WDT disabled (ATtiny12)
<1 2 µA
Power Down
(5)
, V
CC
= 3V.
WDT disabled (ATtiny11)
<1 5 µA
V
ACIO
Analog Comparator
Input Offset Voltage
V
CC
= 5V
V
IN
= V
CC
/2
40 mV
I
ACLK
Analog Comparator
Input Leakage Current
V
CC
= 5V
V
IN
= V
CC
/2
-50 50 nA
T
ACPD
Analog Comparator
Propagation Delay
V
CC
= 2.7V
V
CC
= 4.0V
750
500
ns
DC Characteristics – Preliminary Data (Continued)
T
A
= -40°C to 85°C, V
CC
= 2.7V to 5.5V for ATtiny11, V
CC
= 1.8V to 5.5V for ATtiny12 (Unless otherwise noted)
Symbol Parameter Condition Min Typ Max Units