Datasheet
Table Of Contents
- Features
- Pin Configuration
- Description
- Architectural Overview
- General-purpose Register File
- ALU – Arithmetic Logic Unit
- Flash Program Memory
- Program and Data Addressing Modes
- Subroutine and Interrupt Hardware Stack
- EEPROM Data Memory
- Memory Access and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- ATtiny12 Internal Voltage Reference
- Interrupt Handling
- Sleep Modes for the ATtiny11
- Sleep Modes for the ATtiny12
- ATtiny12 Calibrated Internal RC Oscillator
- Timer/Counter0
- Watchdog Timer
- ATtiny12 EEPROM Read/Write Access
- Analog Comparator
- I/O Port B
- Memory Programming
- Program (and Data) Memory Lock Bits
- Fuse Bits in ATtiny11
- Fuse Bits in ATtiny12
- Signature Bytes
- Calibration Byte in ATtiny12
- Programming the Flash and EEPROM
- High-voltage Serial Programming
- High-voltage Serial Programming Algorithm
- High-voltage Serial Programming Characteristics
- Low-voltage Serial Downloading (ATtiny12 only)
- Low-voltage Serial Programming Characteristics
- Electrical Characteristics
- Register Summary ATtiny11
- Register Summary ATtiny12
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Data Sheet Change Log for ATtiny11/12
- Table of Contents

56
ATtiny11/12
1006D–AVR–07/03
Low-voltage Serial
Programming
Characteristics
Figure 32. Low-voltage Serial Programming Timing
Table 26. Low-voltage Serial Programming Characteristics T
A
= -40°C to 85°C,
V
CC
= 2.2 - 5.5V (Unless otherwise noted)
Symbol Parameter Min Typ Max Units
1/t
CLCL
Oscillator Frequency (V
CC
= 2.2 - 2.7V) 0 1 MHz
t
CLCL
Oscillator Period (V
CC
= 2.2 - 2.7V) 1000 ns
1/t
CLCL
Oscillator Frequency (V
CC
= 2.7 - 4.0V) 0 4 MHz
t
CLCL
Oscillator Period (V
CC
= 2.7 - 4.0V) 250 ns
1/t
CLCL
Oscillator Frequency (V
CC
= 4.0 - 5.5V) 0 8 MHz
t
CLCL
Oscillator Period (V
CC
= 4.0 - 5.5V) 125 ns
t
SHSL
SCK Pulse Width High 2 t
CLCL
ns
t
SLSH
SCK Pulse Width Low 2 t
CLCL
ns
t
OVSH
MOSI Setup to SCK High t
CLCL
ns
t
SHOX
MOSI Hold after SCK High 2 t
CLCL
ns
t
SLIV
SCK Low to MISO Valid 10 16 32 ns
Table 27. Minimum Wait Delay after the Chip Erase Instruction
Symbol Minimum Wait Delay
t
WD_ERASE
6.8 ms
Table 28. Minimum Wait Delay after Writing a Flash or EEPROM Location
Symbol Minimum Wait Delay
t
WD_FLASH
3.4 ms
t
WD_EEPROM
6.8 ms
MOSI
MISO
SCK
t
OVSH
t
SHSL
t
SLSH
t
SHOX
t
SLIV