Datasheet
Table Of Contents
- Features
- Pin Configuration
- Description
- Architectural Overview
- General-purpose Register File
- ALU – Arithmetic Logic Unit
- Flash Program Memory
- Program and Data Addressing Modes
- Subroutine and Interrupt Hardware Stack
- EEPROM Data Memory
- Memory Access and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- ATtiny12 Internal Voltage Reference
- Interrupt Handling
- Sleep Modes for the ATtiny11
- Sleep Modes for the ATtiny12
- ATtiny12 Calibrated Internal RC Oscillator
- Timer/Counter0
- Watchdog Timer
- ATtiny12 EEPROM Read/Write Access
- Analog Comparator
- I/O Port B
- Memory Programming
- Program (and Data) Memory Lock Bits
- Fuse Bits in ATtiny11
- Fuse Bits in ATtiny12
- Signature Bytes
- Calibration Byte in ATtiny12
- Programming the Flash and EEPROM
- High-voltage Serial Programming
- High-voltage Serial Programming Algorithm
- High-voltage Serial Programming Characteristics
- Low-voltage Serial Downloading (ATtiny12 only)
- Low-voltage Serial Programming Characteristics
- Electrical Characteristics
- Register Summary ATtiny11
- Register Summary ATtiny12
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Data Sheet Change Log for ATtiny11/12
- Table of Contents

54
ATtiny11/12
1006D–AVR–07/03
next instruction. See Table 28 on page 56 for t
WD_FLASH
and t
WD_EEPROM
values. In
an erased device, no $FFs in the data file(s) needs to be programmed.
6. Any memory location can be verified by using the Read instruction which returns
the content at the selected address at the serial output MISO (PB1) pin.
7. At the end of the programming session, RESET
can be set high to commence
normal operation.
8. Power-off sequence (if needed):
Set XTAL1 to “0” (if external clocking is used).
Set RESET
to “1”.
Turn V
CC
power off.
Data Polling When a byte is being programmed into the Flash or EEPROM, reading the address
location being programmed will give the value $FF. At the time the device is ready for a
new byte, the programmed value will read correctly. This is used to determine when the
next byte can be written. This will not work for the value $FF, so when programming this
value, the user will have to wait for at least t
WD_FLASH
or t
WD_EEPROM
before programming
the next byte. As a chip-erased device contains $FF in all locations, programming of
addresses that are meant to contain $FF can be skipped. This does not apply if the
EEPROM is reprogrammed without chip-erasing the device. In that case, data polling
cannot be used for the value $FF, and the user will have to wait at least t
WD_EEPROM
before programming the next byte. See Table 28 for t
WD_FLASH
and t
WD_EEPROM
values.
Figure 31. Low-voltage Serial Programming Waveforms
MSB
MSB
LSB
LSB
SERIAL CLOCK INPUT
PB2(SCK)
SERIAL DATA INPUT
PB0(MOSI)
SERIAL DATA OUTPUT
PB1(MISO)