Datasheet
Table Of Contents
- Features
- Pin Configuration
- Description
- Architectural Overview
- General-purpose Register File
- ALU – Arithmetic Logic Unit
- Flash Program Memory
- Program and Data Addressing Modes
- Subroutine and Interrupt Hardware Stack
- EEPROM Data Memory
- Memory Access and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- ATtiny12 Internal Voltage Reference
- Interrupt Handling
- Sleep Modes for the ATtiny11
- Sleep Modes for the ATtiny12
- ATtiny12 Calibrated Internal RC Oscillator
- Timer/Counter0
- Watchdog Timer
- ATtiny12 EEPROM Read/Write Access
- Analog Comparator
- I/O Port B
- Memory Programming
- Program (and Data) Memory Lock Bits
- Fuse Bits in ATtiny11
- Fuse Bits in ATtiny12
- Signature Bytes
- Calibration Byte in ATtiny12
- Programming the Flash and EEPROM
- High-voltage Serial Programming
- High-voltage Serial Programming Algorithm
- High-voltage Serial Programming Characteristics
- Low-voltage Serial Downloading (ATtiny12 only)
- Low-voltage Serial Programming Characteristics
- Electrical Characteristics
- Register Summary ATtiny11
- Register Summary ATtiny12
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Data Sheet Change Log for ATtiny11/12
- Table of Contents

52
ATtiny11/12
1006D–AVR–07/03
High-voltage Serial
Programming
Characteristics
Figure 29. High-voltage Serial Programming Timing
Low-voltage Serial
Downloading (ATtiny12
only)
Both the program and data memory arrays can be programmed using the SPI bus while
RESET
is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and
MISO (output), see Figure 30. After RESET
is set low, the Programming Enable instruc-
tion needs to be executed first before program/erase instructions can be executed.
Figure 30. Serial Programming and Verify
Table 24. High-voltage Serial Programming Characteristics T
A
= 25°C ± 10%, V
CC
=
5.0V ± 10% (Unless otherwise noted)
Symbol Parameter Min Typ Max Units
t
SHSL
SCI (PB3) Pulse Width High 100 ns
t
SLSH
SCI (PB3) Pulse Width Low 100 ns
t
IVSH
SDI (PB0), SII (PB1) Valid to SCI (PB3) High 50 ns
t
SHIX
SDI (PB0), SII (PB1) Hold after SCI (PB3) High 50 ns
t
SHOV
SCI (PB3) High to SDO (PB2) Valid 10 16 32 ns
t
WLWH_PFB
Wait after Instr. 3 for Write Fuse Bits 1.7 2.5 3.4 ms
SDI (PB0), SII (PB1)
SDO (PB2)
SCI (PB3)
t
IVSH
t
SHSL
t
SLSH
t
SHIX
t
SHOV
PB5 (RESET) VCC
PB2
PB1
PB0
SCK
MISO
MOSI
2.2 - 5.5V
GND
ATtiny12
GND