Datasheet
Table Of Contents
- Features
- Pin Configuration
- Description
- Architectural Overview
- General-purpose Register File
- ALU – Arithmetic Logic Unit
- Flash Program Memory
- Program and Data Addressing Modes
- Subroutine and Interrupt Hardware Stack
- EEPROM Data Memory
- Memory Access and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- ATtiny12 Internal Voltage Reference
- Interrupt Handling
- Sleep Modes for the ATtiny11
- Sleep Modes for the ATtiny12
- ATtiny12 Calibrated Internal RC Oscillator
- Timer/Counter0
- Watchdog Timer
- ATtiny12 EEPROM Read/Write Access
- Analog Comparator
- I/O Port B
- Memory Programming
- Program (and Data) Memory Lock Bits
- Fuse Bits in ATtiny11
- Fuse Bits in ATtiny12
- Signature Bytes
- Calibration Byte in ATtiny12
- Programming the Flash and EEPROM
- High-voltage Serial Programming
- High-voltage Serial Programming Algorithm
- High-voltage Serial Programming Characteristics
- Low-voltage Serial Downloading (ATtiny12 only)
- Low-voltage Serial Programming Characteristics
- Electrical Characteristics
- Register Summary ATtiny11
- Register Summary ATtiny12
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Data Sheet Change Log for ATtiny11/12
- Table of Contents

46
ATtiny11/12
1006D–AVR–07/03
Memory
Programming
Program (and Data)
Memory Lock Bits
The ATtiny11/12 MCU provides two lock bits which can be left unprogrammed (“1”) or
can be programmed (“0”) to obtain the additional features listed in Table 21. The lock
bits can only be erased with the Chip Erase command
.
Note: 1. In the High-voltage Serial Programming mode, further programming of the fuse bits
are also disabled. Program the fuse bits before programming the lock bits.
Fuse Bits in ATtiny11 The ATtiny11 has five fuse bits, FSTRT, RSTDISBL and CKSEL2..0.
• FSTRT: See Table 7, “Start-up Times for the ATtiny11 (V
CC
= 2.7V),” on page 18 for
which value to use. Default value is unprogrammed (“1”).
• When RSTDISBL is programmed (“0”), the external reset function of pin PB5 is
disabled.
(1)
Default value is unprogrammed (“1”).
• CKSEL2..0: See Table 3, “Device Clocking Options Select,” on page 5, for which
combination of CKSEL2..0 to use. Default value is “100”, internal RC oscillator.
The status of the fuse bits is not affected by Chip Erase.
Note: 1. If the RSTDISBL Fuse is programmed, then the programming hardware should apply
+12V to PB5 while the ATtiny11 is in Power-on Reset. If not, the part can fail to enter
programming mode caused by drive contention on PB0.
Fuse Bits in ATtiny12 The ATtiny12 has eight fuse bits, BODLEVEL, BODEN, SPIEN, RSTDISBL and
CKSEL3..0. All the fuse bits are programmable in both High-voltage and Low-voltage
Serial programming modes. Changing the fuses does not have any effect while in pro-
gramming mode.
• The BODLEVEL Fuse selects the Brown-out Detection level and changes the start-
up times. See “Brown-out Detection (ATtiny12)” on page 22. See Table 9, “ATtiny12
Clock Options and Start-up Times,” on page 20. Default value is programmed (“0”).
• When the BODEN Fuse is programmed (“0”), the Brown-out Detector is enabled.
See “Brown-out Detection (ATtiny12)” on page 22. Default value is unprogrammed
(“1”).
• When the SPIEN Fuse bit is programmed (“0”), Low-Voltage Serial Program and
Data Downloading is enabled. Default value is programmed (“0”). Unprogramming
this fuse while in the Low-Voltage Serial Programming mode will disable future in-
system downloading attempts.
• When the RSTDISBL Fuse is programmed (“0”), the external reset function of pin
PB5 is disabled.
(1)
Default value is unprogrammed (“1”). Programming this fuse
while in the Low-Voltage Serial Programming mode will disable future in-system
downloading attempts.
Table 21. Lock Bit Protection Modes
Memory Lock Bits
Protection TypeMode LB1 LB2
1 1 1 No memory lock features enabled.
201
Further programming of the Flash (and EEPROM for ATtiny12) is
disabled.
(1)
3 0 0 Same as mode 2, and verify is also disabled.