Datasheet
Table Of Contents
- Features
- Pin Configuration
- Description
- Architectural Overview
- General-purpose Register File
- ALU – Arithmetic Logic Unit
- Flash Program Memory
- Program and Data Addressing Modes
- Subroutine and Interrupt Hardware Stack
- EEPROM Data Memory
- Memory Access and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- ATtiny12 Internal Voltage Reference
- Interrupt Handling
- Sleep Modes for the ATtiny11
- Sleep Modes for the ATtiny12
- ATtiny12 Calibrated Internal RC Oscillator
- Timer/Counter0
- Watchdog Timer
- ATtiny12 EEPROM Read/Write Access
- Analog Comparator
- I/O Port B
- Memory Programming
- Program (and Data) Memory Lock Bits
- Fuse Bits in ATtiny11
- Fuse Bits in ATtiny12
- Signature Bytes
- Calibration Byte in ATtiny12
- Programming the Flash and EEPROM
- High-voltage Serial Programming
- High-voltage Serial Programming Algorithm
- High-voltage Serial Programming Characteristics
- Low-voltage Serial Downloading (ATtiny12 only)
- Low-voltage Serial Programming Characteristics
- Electrical Characteristics
- Register Summary ATtiny11
- Register Summary ATtiny12
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Data Sheet Change Log for ATtiny11/12
- Table of Contents
41
ATtiny11/12
1006D–AVR–07/03
Analog Comparator The Analog Comparator compares the input values on the positive input PB0 (AIN0) and
negative input PB1 (AIN1). When the voltage on the positive input PB0 (AIN0) is higher
than the voltage on the negative input PB1 (AIN1), the Analog Comparator Output
(ACO) is set (one). The comparator’s output can trigger a separate interrupt, exclusive
to the Analog Comparator. The user can select interrupt triggering on comparator output
rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown
in Figure 26.
Figure 26. Analog Comparator Block Diagram.
Analog Comparator Control
and Status Register – ACSR
Note: AINBG is only available in ATtiny12.
• Bit 7 - ACD: Analog Comparator Disable
When this bit is set (one), the power to the Analog Comparator is switched off. This bit
can be set at any time to turn off the Analog Comparator. When changing the ACD bit,
the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR.
Otherwise an interrupt can occur when the bit is changed.
• Bit 6 - AINBG: Analog Comparator Bandgap Select in ATtiny12
In ATtiny12, when this bit is set, a fixed bandgap voltage of 1.22 ± 0.05V replaces the
normal input to the positive input (AIN0) of the comparator. When this bit is cleared, the
normal input pin PB0 is applied to the positive input of the comparator.
• Bit 6- Res: Reserved Bit in ATtiny11
This bit is a reserved bit in the ATtiny11 and will always read as zero.
• Bit 5 - ACO: Analog Comparator Output
ACO is directly connected to the comparator output.
• Bit 4 - ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined
by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit
is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when execut-
INTERNAL
VOLTAGE
REFERENCE
(ATtiny12 ONLY)
MUX
AINBG
Bit 76 543210
$08 ACD (AINBG) ACO ACI ACIE - ACIS1 ACIS0 ACSR
Read/Write R/W R(/W) R R/W R/W R R/W R/W
Initial Value 0 0 X 0 0 0 0 0