Datasheet
Table Of Contents
- Features
- Pin Configuration
- Description
- Architectural Overview
- General-purpose Register File
- ALU – Arithmetic Logic Unit
- Flash Program Memory
- Program and Data Addressing Modes
- Subroutine and Interrupt Hardware Stack
- EEPROM Data Memory
- Memory Access and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- ATtiny12 Internal Voltage Reference
- Interrupt Handling
- Sleep Modes for the ATtiny11
- Sleep Modes for the ATtiny12
- ATtiny12 Calibrated Internal RC Oscillator
- Timer/Counter0
- Watchdog Timer
- ATtiny12 EEPROM Read/Write Access
- Analog Comparator
- I/O Port B
- Memory Programming
- Program (and Data) Memory Lock Bits
- Fuse Bits in ATtiny11
- Fuse Bits in ATtiny12
- Signature Bytes
- Calibration Byte in ATtiny12
- Programming the Flash and EEPROM
- High-voltage Serial Programming
- High-voltage Serial Programming Algorithm
- High-voltage Serial Programming Characteristics
- Low-voltage Serial Downloading (ATtiny12 only)
- Low-voltage Serial Programming Characteristics
- Electrical Characteristics
- Register Summary ATtiny11
- Register Summary ATtiny12
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Data Sheet Change Log for ATtiny11/12
- Table of Contents
38
ATtiny11/12
1006D–AVR–07/03
ATtiny12 EEPROM
Read/Write Access
The EEPROM access registers are accessible in the I/O space.
The write access time is in the range of 3.1 - 6.8 ms, depending on the frequency of the
calibrated RC oscillator. See Table 17 for details. A self-timing function lets the user
software detect when the next byte can be written. A special EEPROM Ready interrupt
can be set to trigger when the EEPROM is ready to accept new data. The minimum volt-
age for writing to the EEPROM is 2.2V.
In order to prevent unintentional EEPROM writes, a two-state write procedure must be
followed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed. When the EEPROM is read, the CPU is halted for four clock
cycles before the next instruction is executed.
EEPROM Address Register –
EEAR
The EEPROM Address Register – EEAR specifies the EEPROM address in the 64-byte
EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 63.
During reset, the EEAR register is not cleared. Instead, the data in the register is kept.
EEPROM Data Register –
EEDR
• Bits 7..0 - EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR register contains the data to be written to
the EEPROM in the address given by the EEAR register. For the EEPROM read opera-
tion, the EEDR contains the data read out from the EEPROM at the address given by
EEAR.
EEPROM Control Register –
EECR
• Bit 7..4 - Res: Reserved Bits
These bits are reserved bits in the ATtiny12 and will always read as zero.
• Bit 3 - EERIE: EEPROM Ready Interrupt Enable
When the I-bit in SREG and EERIE are set (one), the EEPROM Ready interrupt is
enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready interrupt
generates a constant interrupt when EEWE is cleared (zero).
Bit 76543210
$1E - - EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEAR
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 X X X X X X
Bit 76543210
$1D MSB LSB EEDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
$1C - - - - EERIE EEMWE EEWE EERE EECR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 X 0