Datasheet

37
ATtiny11/12
1006D–AVR–07/03
1. In the same operation, write a logical one to WDTOE and WDE. A logical one
must be written to WDE even though it is set to one before the disable operation
starts.
2. Within the next four clock cycles, write a logical 0 to WDE. This disables the
watchdog.
• Bits 2..0 - WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
time-out periods are shown in Table 16.
Note: The frequency of the Watchdog Oscillator is voltage dependent as shown in the section
“ATtiny11 Typical Characteristics” on page 60.
The WDR – Watchdog Reset – instruction should always be executed before the Watch-
dog Timer is enabled. This ensures that the reset period will be in accordance with the
Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the
Watchdog Timer may not start counting from zero.
To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset
before changing the Watchdog Timer Prescale Select.
Table 16. Watchdog Timer Prescale Select
WDP2 WDP1 WDP0
Number of WDT
Oscillator cycles
Typical
Time-out at
V
CC
= 2.0V
Typical
Time-out at
V
CC
= 3.0V
Typical
Time-out at
V
CC
= 5.0V
0 0 0 16K cycles 0.15s 47 ms 15 ms
0 0 1 32K cycles 0.30s 94 ms 30 ms
0 1 0 64K cycles 0.60s 0.19 s 60 ms
0 1 1 128K cycles 1.2s 0.38 s 0.12 s
1 0 0 256K cycles 2.4s 0.75 s 0.24 s
1 0 1 512K cycles 4.8s 1.5 s 0.49 s
1 1 0 1,024K cycles 9.6s 3.0 s 0.97 s
1 1 1 2,048K cycles 19s 6.0 s 1.9 s