Datasheet
Table Of Contents
- Features
- Pin Configuration
- Description
- Architectural Overview
- General-purpose Register File
- ALU – Arithmetic Logic Unit
- Flash Program Memory
- Program and Data Addressing Modes
- Subroutine and Interrupt Hardware Stack
- EEPROM Data Memory
- Memory Access and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- ATtiny12 Internal Voltage Reference
- Interrupt Handling
- Sleep Modes for the ATtiny11
- Sleep Modes for the ATtiny12
- ATtiny12 Calibrated Internal RC Oscillator
- Timer/Counter0
- Watchdog Timer
- ATtiny12 EEPROM Read/Write Access
- Analog Comparator
- I/O Port B
- Memory Programming
- Program (and Data) Memory Lock Bits
- Fuse Bits in ATtiny11
- Fuse Bits in ATtiny12
- Signature Bytes
- Calibration Byte in ATtiny12
- Programming the Flash and EEPROM
- High-voltage Serial Programming
- High-voltage Serial Programming Algorithm
- High-voltage Serial Programming Characteristics
- Low-voltage Serial Downloading (ATtiny12 only)
- Low-voltage Serial Programming Characteristics
- Electrical Characteristics
- Register Summary ATtiny11
- Register Summary ATtiny12
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Data Sheet Change Log for ATtiny11/12
- Table of Contents

31
ATtiny11/12
1006D–AVR–07/03
Sleep Modes for the
ATtiny11
To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc-
tion must be executed. The SM bit in the MCUCR register selects which sleep mode
(Idle or Power-down) will be activated by the SLEEP instruction. If an enabled interrupt
occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt rou-
tine, and resumes execution from the instruction following SLEEP. On wake-up from
Power Down Mode on pin change, two instruction cycles are executed before the pin
change interrupt flag is updated. During these cycles, the prosessor executes intruc-
tions, but the interrupt condition is not readable, and the interrupt routine has not startet
yet. The contents of the register file and I/O memory are unaltered. If a reset occurs dur-
ing Sleep Mode, the MCU wakes up and executes from the Reset vector.
Idle Mode When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle
Mode, stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt sys-
tem to continue operating. This enables the MCU to wake up from external triggered
interrupts as well as internal ones like Timer Overflow interrupt and Watchdog Reset. If
wake-up from the Analog Comparator interrupt is not required, the analog comparator
can be powered down by setting the ACD-bit in the Analog Comparator Control and Sta-
tus register – ACSR. This will reduce power consumption in Idle Mode. When the MCU
wakes up from Idle mode, the CPU starts program execution immediately.
Power-down Mode When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power-
down Mode. In this mode, the external oscillator is stopped, while the external interrupts
and the Watchdog (if enabled) continue operating. Only an external reset, a watchdog
reset (if enabled), an external level interrupt, or an pin change interrupt can wake up the
MCU.
Note that if a level-triggered or pin change interrupt is used for wake-up from power-
down, the changed level must be held for a time longer than the reset delay period of
t
TOUT
. Otherwise, the MCU will fail to wake up.
Sleep Modes for the
ATtiny12
To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc-
tion must be executed. The SM bit in the MCUCR register selects which sleep mode
(Idle or Power-down) will be activated by the SLEEP instruction. If an enabled interrupt
occurs while the MCU is in a sleep mode, the MCU awakes. The CPU is then halted for
four cycles, it executes the interrupt routine, and resumes execution from the instruction
following SLEEP. The contents of the register file and I/O memory are unaltered. If a
reset occurs during sleep mode, the MCU wakes up and executes from the Reset
vector.
Idle Mode When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle
Mode stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt sys-
tem to continue operating. This enables the MCU to wake up from external triggered
interrupts as well as internal ones like Timer Overflow interrupt and Watchdog Reset. If
wake-up from the Analog Comparator interrupt is not required, the analog comparator
can be powered down by setting the ACD-bit in the Analog Comparator Control and Sta-
tus Register – ACSR. This will reduce power consumption in Idle Mode.
Power-down Mode When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power-
down Mode. In this mode, the external oscillator is stopped, while the external interrupts
and the Watchdog (if enabled) continue operating. Only an external reset, a watchdog
reset (if enabled), an external level interrupt, or a pin change interrupt can wake up the
MCU.