Datasheet
Table Of Contents
- Features
- Pin Configuration
- Description
- Architectural Overview
- General-purpose Register File
- ALU – Arithmetic Logic Unit
- Flash Program Memory
- Program and Data Addressing Modes
- Subroutine and Interrupt Hardware Stack
- EEPROM Data Memory
- Memory Access and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- ATtiny12 Internal Voltage Reference
- Interrupt Handling
- Sleep Modes for the ATtiny11
- Sleep Modes for the ATtiny12
- ATtiny12 Calibrated Internal RC Oscillator
- Timer/Counter0
- Watchdog Timer
- ATtiny12 EEPROM Read/Write Access
- Analog Comparator
- I/O Port B
- Memory Programming
- Program (and Data) Memory Lock Bits
- Fuse Bits in ATtiny11
- Fuse Bits in ATtiny12
- Signature Bytes
- Calibration Byte in ATtiny12
- Programming the Flash and EEPROM
- High-voltage Serial Programming
- High-voltage Serial Programming Algorithm
- High-voltage Serial Programming Characteristics
- Low-voltage Serial Downloading (ATtiny12 only)
- Low-voltage Serial Programming Characteristics
- Electrical Characteristics
- Register Summary ATtiny11
- Register Summary ATtiny12
- Instruction Set Summary
- Ordering Information
- Packaging Information
- Data Sheet Change Log for ATtiny11/12
- Table of Contents
23
ATtiny11/12
1006D–AVR–07/03
Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle dura-
tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period
(t
TOUT
). Refer to page 36 for details on operation of the Watchdog.
Figure 22. Watchdog Reset during Operation
MCU Status Register –
MCUSR of the ATtiny11
The MCU Status Register provides information on which reset source caused an MCU
reset.
• Bit 7..2 - Res: Reserved Bits
These bits are reserved bits in the ATtiny11 and always read as zero.
• Bit 1 - EXTRF: EXTernal Reset Flag
After a power-on reset, this bit is undefined (X). It will be set by an external reset. A
watchdog reset will leave this bit unchanged.
• Bit 0 - PORF: Power-on Reset Flag
This bit is set by a power-on reset. A watchdog reset or an external reset will leave this
bit unchanged.
To summarize, the following table shows the value of these two bits after the three
modes of reset.
To identify a reset condition, the user software should clear both the PORF and EXTRF
bits as early as possible in the program. Checking the PORF and EXTRF values is done
CK
V
CC
Bit 76543210
$34 ------EXTRFPORFMCUSR
Read/WriteRRRRRRR/WR/W
Initial Value000000See bit description
Table 11. PORF and EXTRF Values after Reset
Reset Source EXTRF PORF
Power-on Undefined 1
External Reset 1 Unchanged
Watchdog Reset Unchanged Unchanged